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LMH6586VS/NOPB Datasheet(PDF) 27 Page - Texas Instruments |
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LMH6586VS/NOPB Datasheet(HTML) 27 Page - Texas Instruments |
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27 / 35 page  LMH6586 www.ti.com SNCS105D – JULY 2008 – REVISED MARCH 2013 Table 4. Video and Sync Detection Control Registers Register Address R/W Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESERVED 0x08h R/W 0x00 RSV RSV RSV RSV RSV RSV RSV RSV 0x0Bh VIDEO DETECT 0x0Ch R/W 0x00 VD_ VD_ VD_ VD_ VD_ VD_ VD_ VD_ INVERT (CH 0-7) INV_7 INV_6 INV_5 INV_4 INV_3 INV_2 INV_1 INV_0 VIDEO DETECT 0x0Dh R/W 0x00 VD_ VD_ VD_ VD_ VD_ VD_ VD_ VD_ INVERT (CH 8-15) INV_15 INV_14 INV_13 INV_12 INV_11 INV_10 INV_9 INV_8 VIDEO DETECT 0x0Eh R/W 0x00 VD_ VD_ VD_ VD_ VD_ VD_ VD_ VD_ INVERT (CH 16-23) INV_23 INV_22 INV_21 INV_20 INV_19 INV_18 INV_17 INV_16 VIDEO DETECT 0x0Fh R/W 0x00 VD_ VD_ VD_ VD_ VD_ VD_ VD_ VD_ INVERT (CH 24-31) INV_31 INV_30 INV_29 INV_28 INV_27 INV_26 INV_24 INV_24 SYNC DETECT 0x10h R/W 0x00 SD_ SD_ SD_ SD_ SD_ SD_ SD_ SD_ ENABLE (CH 0-7) EN_7 EN_6 EN_5 EN_4 EN_3 EN_2 EN_1 EN_0 SYNC DETECT 0x11h R/W 0x00 SD_ SD_ SD_ SD_ SD_ SD_ SD_ SD_ ENABLE (CH 8-15) EN_15 EN_14 EN_13 EN_12 EN_11 EN_10 EN_9 EN_8 SYNC DETECT 0x12h R/W 0x00 SD_ SD_ SD_ SD_ SD_ SD_ SD_ SD_ ENABLE (CH 16-23) EN_23 EN_22 EN_21 EN_20 EN_19 EN_18 EN_17 EN_16 SYNC DETECT 0x13h R/W 0x00 SD_ SD_ SD_ SD_ SD_ SD_ SD_ SD_ ENABLE (CH 24-31) EN_31 EN_30 EN_29 EN_28 EN_27 EN_26 EN_25 EN_24 VIDEO DETECT 0x14h R/W 0x00 VD_ VD_ VD_ VD_ VD_ VD_ VD_ VD_ ENABLE (CH 0-7) EN_7 EN_6 EN_5 EN_4 EN_3 EN_2 EN_1 EN_0 VIDEO DETECT 0x15h R/W 0x00 VD_ VD_ VD_ VD_ VD_ VD_ VD_ VD_ ENABLE (CH 8-15) EN_15 EN_14 EN_13 EN_12 EN_11 EN_10 EN_9 EN_8 VIDEO DETECT 0x16h R/W 0x00 VD_ VD_ VD_ VD_ VD_ VD_ VD_ VD_ ENABLE (CH 16-23) EN_23 EN_22 EN_21 EN_20 EN_19 EN_18 EN_17 EN_16 VIDEO DETECT 0x17h R/W 0x00 VD_ VD_ VD_ VD_ VD_ VD_ VD_ SD_ ENABLE (CH 24-31) EN_31 EN_30 EN_29 EN_28 EN_27 EN_26 EN_25 EN_24 Table 5. Video Detection Threshold Control Registers Register Address R/W Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VIDEO DETECT 0x1Dh R/W 0x00 RSV VDT[2:0] THRESHOLD Table 6. Input and Output Shutdown Registers Register Address R/W Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INPUT SHUTDOWN 0x18h R/W 0x00 IN_ IN_ IN_ IN_ IN_ IN_ IN_ IN_ (CH 0-7) PS_7 PS_6 PS_5 PS_4 PS_3 PS_2 PS_1 PS_0 INPUT SHUTDOWN 0x19h R/W 0x00 IN_ IN_ IN_ IN_ IN_ IN_ IN_ IN_ (CH 8-15) PS_15 PS_14 PS_13 PS_12 PS_11 PS_10 PS_9 PS_8 INPUT SHUTDOWN 0x1Ah R/W 0x00 IN_ IN_ IN_ IN_ IN_ IN_ IN_ IN_ (CH 16-23) PS_23 PS_22 PS_21 PS_20 PS_19 PS_18 PS_17 PS_16 INPUT SHUTDOWN 0x1Bh R/W 0x00 IN_ IN_ IN_ IN_ IN_ IN_ IN_ IN_ (CH 24-31) PS_31 PS_30 PS_29 PS_28 PS_27 PS_26 PS_25 PS_24 OUTPUT 0x1Eh R/W 0x00 OUT_ OUT_ OUT_ OUT_ OUT_ OUT_ OUT_ OUT_ SHUTDOWN PS_7 PS_6 PS_5 PS_4 PS_3 PS_2 PS_1 PS_0 (CH 0-7) OUTPUT 0x1Fh R/W 0x00 OUT_ OUT_ OUT_ OUT_ OUT_ OUT_ OUT_ OUT_ SHUTDOWN PS_15 PS_14 PS_13 PS_12 PS_11 PS_10 PS_9 PS_8 (CH 8-15) Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 27 Product Folder Links: LMH6586 |
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