THS7347

SLOS531B

– MAY 2007 – REVISED OCTOBER 2011

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TERMINAL FUNCTIONS (continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

H-SYNC, INPUT B

10

I

Horizontal Sync, Input B

V-SYNC, INPUT B

11

I

Vertical Sync, Input B

I2C Slave Address Control Bit A1. Connect to VDD for a logic 1 preset value or GND for a logic 0 preset

17

I

I2C, A1

value.

I2C Slave Address Control Bit A0. Connect to VDD for a logic 1 preset value or GND for a logic 0 preset

18

I

I2C, A0

value.

Serial data line of the I2C bus. Pull-up resistor should have a minimum value = 2 k

Ω and a maximum value

SDA

19

I/O

= 19 k

Ω. Pull up to VDD.

I2C bus clock line. Pull-up resistor should have a minimum value = 2 k

Ω and a maximum value = 19 -kΩ.

SCL

20

I

Pull up to VDD.

Power-Up Condition. Connect to GND for all channels disabled upon power-up. Connect to VDD (logic

PUC

21

I

high) to set buffer outputs to OFF and monitor outputs ON with ac-bias configuration on Channels 1 to 3

and both H-Sync/V-Sync enabled.

Sets the MUX configuration control. Connect to logic low for MUX Select (pin 16) control of the MUX.

MUX MODE

15

I

Connect to logic high for I2C control of the MUX.

Controls the MUX selection when MUX MODE (pin 15) is set to logic low. Connect to logic low for MUX

MUX SELECT

16

I

selector set to Input A. Connect to logic high for MUX selector set to Input B.

Output Channel 1 from either CH. 1, INPUT A or CH. 1, INPUT B. Connect to ADC/Scalar/Decoder. Both

CH. 1, BUFFER OUTPUT

35, 36

O

pins should be connected together on the PCB.

Output Channel 2 from either CH. 2, INPUT A or CH. 2, INPUT B. Connect to ADC/Scalar/Decoder. Both

CH. 2, BUFFER OUTPUT

31, 32

O

pins should be connected together on the PCB.

Output Channel 3 from either CH. 3, INPUT A or CH. 3, INPUT B. Connect to ADC/Scalar/Decoder. Both

CH. 3, BUFFER OUTPUT

27, 28

O

pins should be connected together on the PCB.

H-SYNC BUFFER

25

O

Horizontal Sync Buffer Output. Connect to ADC/Scalar H-sync input.

OUTPUT

V-SYNC BUFFER

24

O

Vertical Sync Buffer Output. Connect to ADC/Scalar V-sync input.

OUTPUT

Video Monitor Pass-Through Output Channel 1 SAG Correction pin. If SAG is not used, connect Directly to

CH. 1, SAG

45

O

CH. 1, OUTPUT pin 46.

CH. 1, MONITOR

46

O

Video Monitor Pass-Through Output Channel 1 from either CH. 1, INPUT A or CH. 1, INPUT B.

OUTPUT

Video Monitor Pass-Through Output Channel 2 SAG Correction pin. If SAG is not used, connect Directly to

CH. 2, SAG

43

O

CH. 2, OUTPUT pin 44.

CH. 2, MONITOR

44

O

Video Monitor Pass-Through Output Channel 2 from either CH. 2, INPUT A or CH. 2, INPUT B.

OUTPUT

Video Monitor Pass-Through Output Channel 3 SAG Correction pin. If SAG is not used, connect Directly to

CH. 3, SAG

41

O

CH. 3, OUTPUT pin 42.

CH. 3, MONITOR

42

O

Video Monitor Pass-Through Output Channel 3 from either CH. 3, INPUT A or CH. 3, INPUT B.

OUTPUT

H-SYNC MONITOR

40

O

Horizontal Sync Monitor Pass-Through Output.

OUTPUT

V-SYNC MONITOR

39

O

Vertical Sync Monitor Pass-Through Output.

OUTPUT

6, 12, 13, 26,

Ground Reference pin for analog signals. Internally, these pins connect to DGND, although it is

AGND

I

30, 34, 37, 47

recommended to have the AGND and DGND connected to the proper signals for best results.

+VA

29, 33, 38, 48

I

Analog Positive Power Supply Input pins. Connect to 2.7 V to 5 V. Must be equal to or greater than VDD.

VDD

22

I

Digital Positive Supply pin for I2C circuitry and H-Sync/V-Sync outputs. Connect to 2.7 V to 5 V.

DGND

23

I

Digital GND pin for HV circuitry and I2C circuitry.

Defaults to 1.45 V (TTL compatible). Connect to external voltage reference to adjust H-Sync/V-Sync input

Schmitt Trigger Adjust

14

I

thresholds from 0.9 V to 2 V range.

12

Copyright

© 2007–2011, Texas Instruments Incorporated