CS2

SS

20 PA

1 PA

16

LM5025A

SNVS293F – DECEMBER 2004 – REVISED AUGUST 2016

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Feature Description (continued)

The LM5025A CS comparators are very fast and may respond to short duration noise pulses. Layout

considerations are critical for the current sense filter and sense resistor. The capacitor associated with the CS

filter must be placed very close to the device and connected directly to the pins of the IC (CS and GND). If a

current sense transformer is used, both leads of the transformer secondary must be routed to the filter network,

which must be placed close to the IC. If a sense resistor in the source of the main switch MOSFET is used for

current sensing, a low inductance type of resistor is required. When designing with a current sense resistor, all of

the noise-sensitive, low-power ground connections must be connected together near the IC GND and a single

connection must be made to the power ground (sense resistor ground point).

Figure 12. Current Limit

7.3.8 Oscillator and Sync Capability

The LM5025A oscillator is set by a single external resistor connected between the RT pin and GND. To set a

desired oscillator frequency (F), the necessary RT resistor can be calculated in Equation 5:

RT = (5725/F)

1.026

where

•

F is in kHz and RT in kΩ

(5)

The RT resistor must be placed very close to the device and connected directly to the pins of the IC (RT and

GND).

A unique feature of LM5025A is the ability to synchronize the oscillator to an external clock with a frequency that

is either higher or lower than the frequency of the internal oscillator. The lower frequency sync frequency range is

80% of the free-running internal oscillator frequency. There is no constraint on the maximum SYNC frequency. A

minimum pulse width of 100 ns is required for the synchronization clock. If the synchronization feature is not

required, the SYNC pin must be connected to GND to prevent any abnormal interference. The internal oscillator

can be completely disabled by connecting the RT pin to REF. Once disabled, the sync signal acts directly as the

master clock for the controller. Both the frequency and the maximum duty cycle of the PWM controller can be

controlled by the SYNC signal (within the limitations of the Volt × Second Clamp). The maximum duty cycle (D)

will be (1-D) of the SYNC signal.

7.3.9 Feed-Forward Ramp

An external resistor (RFF) and capacitor (CFF) connected to VIN and GND are required to create the PWM ramp

signal. The slope of the signal at the RAMP pin varies in proportion to the input line voltage. This varying slope

provides line feedforward information necessary to improve line transient response with voltage mode control.

The RAMP signal is compared to the error signal at the COMP pin by the pulse width modulator comparator to

control the duty cycle of the main switch output. The Volt Second Clamp comparator also monitors the RAMP pin

and if the ramp amplitude exceeds 2.5 V the present cycle is terminated. The ramp signal is reset to GND at the

end of each cycle by either the internal clock or the Volt Second comparator, which ever occurs first.