6

LM5025A

SNVS293F – DECEMBER 2004 – REVISED AUGUST 2016

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Copyright © 2004–2016, Texas Instruments Incorporated

(1)

All electrical characteristics having room temperature limits are tested during production with TA = TJ = 25°C. All hot and cold limits are

specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

(2)

Device thermal limitations may limit usable range.

6.5 Electrical Characteristics

Typical limits are for TJ = 25°C, and minimum and maximum limits apply over the operating junction temperature range

(–40°C to 125°C). VIN = 48 V, VCC = 10 V, RT = 31.3 kΩ, RSET = 27.4 kΩ) unless otherwise stated

(1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

START-UP REGULATOR

VCC

Reg

VCC regulation

No load

TJ = 25°C

7.6

V

TJ = Tlow to Thigh

7.3

7.9

VCC current limit

See (2)

TJ = 25°C

25

mA

TJ = Tlow to Thigh

20

I-VIN

Start-up regulator leakage

(external Vcc Supply)

VIN = 100 V

TJ = 25°C

165

µA

TJ = Tlow to Thigh

500

VCC SUPPLY

VCC undervoltage lockout

voltage (positive going Vcc)

TJ = 25°C

VCC Reg -

120 mV

V

TJ = Tlow to Thigh

VCC Reg -

220 mV

VCC undervoltage

hysteresis

TJ = 25°C

1.5

V

TJ = Tlow to Thigh

1

2

VCC supply current (ICC)

Cgate = 0

TJ = Tlow to Thigh

4.2

mA

REFERENCE SUPPLY

VREF

Ref voltage

IREF = 0 mA

TJ = 25°C

5

V

TJ = Tlow to Thigh

4.85

5.15

Ref voltage regulation

IREF = 0 to 10mA

TJ = 25°C

25

mV

TJ = Tlow to Thigh

50

Ref current limit

TJ = 25°C

20

mA

TJ = Tlow to Thigh

10

CURRENT LIMIT

CS1

Prop

CS1 delay to output

CS1 Step from 0 to 0.6 V,

Time to onset of OUT Transition (90%),

Cgate = 0

40

ns

CS2

Prop

CS2 delay to output

CS2 Step from 0 to 0.6 V,

Time to onset of OUT Transition (90%),

Cgate = 0

50

ns

Cycle by cycle threshold

voltage (CS1)

TJ = 25°C

0.5

V

over full operating junction temperature

0.45

0.55

Cycle skip threshold voltage

(CS2)

Resets SS capacitor;

auto restart

TJ = 25°C

0.5

V

TJ = Tlow to Thigh

0.45

0.55

Leading edge blanking time

(CS1)

50

ns

CS1 sink impedance

(clocked)

CS1 = 0.4 V

TJ = 25°C

30

Ω

TJ = Tlow to Thigh

50

CS1 sink impedance (post

fault discharge)

CS1 = 0.6 V

TJ = 25°C

15

Ω

TJ = Tlow to Thigh

30

CS2 sink impedance (post

fault discharge)

CS2 = 0.6 V

TJ = 25°C

55

Ω

TJ = Tlow to Thigh

95

CS1 and CS2 leakage

current

CS = CS Threshold –

100 mV

TJ = Tlow to Thigh

1

µA