ADC101S021

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SNAS307G – JULY 2005 – REVISED JANUARY 2014

Modes of Operation

The ADC has two possible modes of operation: normal mode, and shutdown mode. The ADC enters normal

mode (and a conversion process is begun) when CS is pulled low. The device will enter shutdown mode if CS is

pulled high before the tenth falling edge of SCLK after CS is pulled low, or will stay in normal mode if CS remains

low. Once in shutdown mode, the device will stay there until CS is brought low again. By varying the ratio of time

spent in the normal and shutdown modes, a system may trade-off throughput for power consumption, with a

sample rate as low as zero.

Normal Mode

The fastest possible throughput is obtained by leaving the ADC in normal mode at all times, so there are no

power-up delays. To keep the device in normal mode continuously, CS must be kept low until after the 10th

falling edge of SCLK after the start of a conversion (remember that a conversion is initiated by bringing CS low).

If CS is brought high after the 10th falling edge, but before the 16th falling edge, the device will remain in normal

mode, but the current conversion will be aborted, and SDATA will return to TRI-STATE (truncating the output

word).

Sixteen SCLK cycles are required to read all of a conversion word from the device. After sixteen SCLK cycles

have elapsed, CS may be idled either high or low until the next conversion. If CS is idled low, it must be brought

high again before the start of the next conversion, which begins when CS is again brought low.

After sixteen SCLK cycles, SDATA returns to TRI-STATE. Another conversion may be started, after tQUIET has

elapsed, by bringing CS low again.

Shutdown Mode

Shutdown mode is appropriate for applications that either do not sample continuously, or it is acceptable to trade

throughput for power consumption. When the ADC is in shutdown mode, all of the analog circuitry is turned off.

To enter shutdown mode, a conversion must be interrupted by bringing CS high anytime between the second

and tenth falling edges of SCLK, as shown in Figure 21. Once CS has been brought high in this manner, the

device will enter shutdown mode, the current conversion will be aborted and SDATA will enter TRI-STATE. If CS

is brought high before the second falling edge of SCLK, the device will not change mode; this is to avoid

accidentally changing mode as a result of noise on the CS line.

Figure 21. Entering Shutdown Mode

Figure 22. Entering Normal Mode

To exit shutdown mode, bring CS back low. Upon bringing CS low, the ADC will begin powering up (power-up

time is specified in the Timing Specifications table). This power-up delay results in the first conversion result

being unusable. The second conversion performed after power-up, however, is valid, as shown in Figure 22.

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