ADS1610IPAPR.B datasheet(15/29 Pages) TI2

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DATA FORMAT

OUT-OF-RANGE INDICATION (OTR)

DATA RETRIEVAL

SYNCHRONISING MULTIPLE ADS1610s

) VREF

215 * 1

*VREF

215 * 1

*VREF

215

215 * 1

v *VREF

215

215 * 1

ADS1610

SBAS344C – AUGUST 2005 – REVISED OCTOBER 2006

The 16-bit output data is in binary two's complement

If the output code on DOUT[15:0] exceeds the

format, as shown in Table 2. When the input is

positive or negative full-scale, the out-of-range digital

positive

out-of-range,

exceeding

the

positive

output (OTR) will go high on the falling edge of

full-scale value of VREF, the output clips to all 7FFFH

DRDY. When the output code returns within the

and the OTR output goes high.

full-scale range, OTR returns low on the falling edge

of DRDY.

Table 1. Maximum Allowable Clock Source Jitter

for Different Input Signal Frequencies and

Amplitude

Data retrieval is controlled through a simple parallel

INPUT SIGNAL

MAXIMUM

interface. The falling edge of the DRDY output

ALLOWABLE

MAXIMUM

indicates new data is available. To activate the

CLOCK SOURCE

FREQUENCY

AMPLITUDE

output bus, both CS and RD must be low, as shown

JITTER

in Table 3. Make sure the DOUT bus does not drive

4MHz

–1dB

1.6ps

heavy

loads

20pF),

this

will

degrade

4MHz

–20dB

14ps

performance. Use an external buffer when driving an

2MHz

–1dB

3.3ps

edge connector or cables.

2MHz

–20dB

29ps

Table 3. Truth Table for CS and RD

1MHz

–1dB

6.5ps

1MHz

–20dB

58ps

DOUT [15:0]

100kHz

–1dB

65ps

Active

100kHz

–20dB

581ps

High impedance

Table 2. Output Code Versus Input Signal

High impedance

INPUT SIGNAL

IDEAL OUTPUT

OTR

(INP – INN)

CODE(1)

≥ +V

ref (> 0dB)

7FFFH

The ADS1610 is asynchronously reset when the

Vref (0dB)

7FFFH

SYNC pin is taken low. During reset, all of the digital

0001H

circuits are cleared, DOUT[15:0] are forced low, and

DRDY forced high. It is recommended that the SYNC

pin be released on the falling edge of CLK.

0000H

Afterwards, DRDY goes low on the second rising

FFFFH

edge of CLK. Allow 55 DRDY cycles for the digital

filter to settle before retrieving data. See Figure 3 for

8000H

the timing specifications.

Reset

can

used

synchronize

multiple

8000H

ADS1610s. All devices to be synchronized must use

a common CLK input. With the CLK inputs running,

(1)Excludes effects of noise, INL, offset and gain errors.

pulse SYNC on the falling edge of CLK, as shown in

Figure

31.

Afterwards,

the

converters

will

Likewise, when the input is negative out-of-range by

converting synchronously with the DRDY outputs

going below the negative full-scale value of Vref, the

updating simultaneously. After synchronization, allow

output clips to 8000H and the OTR output goes high.

55 DRDY cycles (t11) for output data to fully settle.

The OTR remains high while the input signal is

out-of-range.

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