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STW4810CHDRLF Datasheet(PDF) 61 Page - STMicroelectronics |
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STW4810CHDRLF Datasheet(HTML) 61 Page - STMicroelectronics |
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61 / 78 page ![]() STw4810 Electrical and timing characteristics 61/78 5.4.4 CMOS input/output static characteristics: VBAT level Table 48. CMOS input/output static characteristics: VBAT level Symbol Description Test conditions Min. Typ. Max. Units IT_WAKE_UP, PON, GPO1, GPO2 VIL Low level input voltage PON 0.3*Vbat V VIH High level input voltage PON 0.7*Vbat V IIL Low level input current PON -1.0 1.5 µA IIH High level input current PON -1.0 1.5 µA CIN Input capacitance 10 pF VOL Low level output voltage IT_WAKE_UP, GPO1, GPO2 IOL = 2mA 0.2*Vbat V VOH High level output voltage IT_WAKE_UP, GPO1, GPO2 IOL = 2 mA 0.8*Vbat V tOF Output fall time Capacitance 10pF 5 ns tOR Output rise time Capacitance 10pF 50 ns CI/O Driving capability 100 pF |
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