MB97R8050

2

DS411-00005-4v0-E



BLOCK DIAGRAM



RF INTERFACE

RF signal interface is compliant with EPCglobal C1G2 Ver.1.2.0 (as described in 6.3.1).



MEMORY

1. Memory addressing

Memory addressing uses Extensible bit vectors (EBV) format, which is compliant with EPCglobal C1G2

Ver1.2.0 (Annex A).

2. Memory Map

(1) Memory area

The memory is divided into the following four areas. There is only 48-bit FeRAM in TID area.

• Four memory areas

Note : Command abbreviation:

R:READ, W: WRITE, S: SELECT, L: Lock, BLW: BlockWrite, BLE: BlockErase

The TID, EPC, and Reserved memory areas contain the data that is defined by the EPCglobal C1G2

specification (Chapter 6.3.2.1). The memory areas are also called as “Memory bank” or “Bank” in EPC

standard.

In each memory bank, the logical address starts from zero (00H).

Logical addressing in EBV-8 format is used.

The system area stores memory lock information.

The memory map is shown in the table on next page. (The system area is not disclosed).

Name

Memory size

BANK

Address range

Access command

TID

11w



16b 

176bit

10

00H to 0AH

R/S

EPC

10w



16b 

160bit

01

00H to 09H

R/W/S/BLW/BLE

Reserved

4w



16b 

64bit

00

00H to 03H

R/W

System

1w



16b 

16bit





L

VDD

R/W

FeRAM

Analog RF interface

Digital control

Rectifier

Clock generator

Power supply

voltage control

Modulator

Demodulator

Anti-collision

function

I/O

Commands

FeRAM access

Clock

Data output

Data input

Data output

Data input

Antenna