SNLS065D datasheet(14/24 Pages) TI2

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DS90CF388A Pin Descriptions — FPD Link Receiver

Pin Name

I/O

No.

Description

AnP

Positive LVDS differential data inputs.

AnM

Negative LVDS differential data inputs.

Rn, Gn, Bn,

DE, HSYNC,

VSYNC

TTL level data outputs. This includes: 16 Red, 16 Green, 16 Blue, and 3

control lines — HSYNC (LP), VSYNC (FLM), DE (Data Enable).

RxCLK INP

Positive LVDS differential clock input.

RxCLK INM

Negative LVDS differential clock input.

RxCLK OUT

TTL level clock output. The falling edge acts as data strobe.

R_FDE

Programmable control (DE) strobe select. Tied high for data active when DE

is high. (Note 10)

PLLSEL

PLL range select. This pin must be tied to V

CC for auto-range. NC or tied to

Ground is reserved for future use. Typical shift point is between 55 and 68

MHz. (Notes 10, 11)

TTL level input. When asserted (low input) the receiver data outputs are low

and clock output is high. (Note 10)

STOPCLK

Indicates receiver clock input signal is not present with a logic high. With a

clock input present, a low logic is indicated.

Power supply pins for TTL outputs and digital circuitry.

GND

Ground pins for TTL outputs and digital circuitry

PLLV

Power supply for PLL circuitry.

PLLGND

Ground pin for PLL circuitry.

LVDSV

Power supply pin for LVDS inputs.

LVDSGND

Ground pins for LVDS inputs.

CNTLE,

CNTLF

No Connect. Make NO Connection to these pins - leave these pins open, do

not tie to ground or V

CC.

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