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DS250DF230ZLSR Datasheet(PDF) 6 Page - Texas Instruments |
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DS250DF230ZLSR Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 119 page  Table 6-1. Pin Functions (continued) PIN TYPE INTERNAL PULL-UP/ PULL- DOWN DESCRIPTION NAME NFBGA QFN GND A3, A4,B1, B2,B5, B6,E1, E2,E5, E6,F3, F4 1, 4, 5, 8, 17, 20, 21, 24 Power None Ground reference. The GND pins on this device must be connected through a low-resistance path to the board GND plane. DAP — DAP Power None DAP is the exposed pad at the bottom of the RTV package. The exposed pad should be connected to the GND plane through a 3x3 via array. DS250DF230 SNLS590C – AUGUST 2018 – REVISED JUNE 2021 www.ti.com 6 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DS250DF230 |
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