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SN75DP130SSRGZRG4 Datasheet(PDF) 32 Page - Texas Instruments |
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SN75DP130SSRGZRG4 Datasheet(HTML) 32 Page - Texas Instruments |
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32 / 55 page  SN75DP130 SLLSE57E – APRIL 2011 – REVISED MARCH 2015 www.ti.com space Table 23. Offset = 1Ch Bit Field Type Description This value maps to bits 19:16 of the 20-bit DPCD register address 3:0 DPCD_ADDR_HIGH RW accessed through the DPCD_DATA register. space Table 24. Offset = 1DH Bit Field Type Description This value maps to bits 15:8 of the 20-bit DPCD register address 7:0 DPCD_ADDR_MID RW accessed through the DPCD_DATA register. space Table 25. Offset = 1Eh Bit Field Type Description This value maps to bits 7:0 of the 20-bit DPCD register address 7:0 DPCD_ADDR_LOW RW accessed through the DPCD_DATA register. space Table 26. Offset = 1Fh Bit Field Type Description This register contains the data to write into or read from the DPCD 7:0 DPCD_DATA RW register addressed by DPCD_ADDR_HIGH, DPCD_ADDR_MID, and DPCD_ADDR_LOW. space Table 27. Offset = 20h Bit Field Type Description This field identifies the device and revision. 7:1 DEV_ID_REV. RO 0000000 – SN75DP130 Revision 0 The value read from this field is the inverse of that written. 0 BIT_INVERT R/W Default read value is zero. space Table 28. Offset = 21h Bit Field Type Description 7:0 TI_TEST R/W These registers shall not be modified. space Table 29. Offset = 22h – 27h Bit Field Type Description 7:0 TI_TEST_RESERVED RO These read only registers are reserved for test; writes are ignored. 32 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN75DP130 |
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