TLV320AIC22CPT.B datasheet(21/56 Pages) TI2

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TLV320AIC22C

DUAL VOICE OVER INTERNET PROTOCOL (VoIP) CODEC

SPAS041B – OCTOBER 2001 – REVISED JANUARY 2003

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Table 4. 4-Bit DAC Input Code vs Output Voltage

INPUT

VALUE

(DECIMAL)

INPUT CODE

(2S COMPLEMENT)

D3–D0

OUTPUT

VOLTAGE

0111

2.8125

0110

2.625

0101

2.4375

0100

2.25

0011

2.0625

0010

1.875

0001

1.6875

0000

1.5

–1

1111

1.3125

–2

1110

1.125

–3

1101

0.9375

–4

1100

0.75

–5

1011

0.5625

–6

1010

0.375

–7

1001

0.1875

–8

1000

caller ID amplifier

The caller ID amplifier has a fixed 0-dB gain (typ), attenuates the low-frequency ring signal, and isolates from

the line. This input also can be connected to the ADC via the analog crosspoint.

line ports

The line ports can be connected, via a transformer, to a telephone line. The driver stage is capable of driving

a 600-

Ω load, differentially, to near rail-to-rail swing. This stage is implemented such that the resistors and

capacitors are integrated. Signal levels at the input terminals can be as high as 1.4 Vrms (2 V). The analog pole

select option (register 14) allows the user to select the position of the filter pole for the line input and output.

serial interface

The serial interface is designed to provide glueless interface to the McBSP of a TMS320C54x

 or TMS320C6x

DSP. This interface is used primarily for transferring ADC and DAC data. However, control register information

also can be transferred, refer to register programming using the serial interface. The serial interface is a 4-line

interface consisting of:

D BCLK – bit clock used to transmit and receive data bits

D FSYNC – frame-synchronization signal that denotes the start of a new frame of data

D DOUT – output serial data used to transfer ADC data and register information to the attached DSP

D DIN – input serial data used to transfer DAC data and register control information from the attached DSP

The TLV320AIC22C can be configured as a master or a slave (see the master/slave functionality section for

a detailed description). When configured as a master device, FSYNC and BCLK are generated by the master

codec and input to the DSP.

Data is received and transmitted in frames consisting of 256 BCLKs, which is 16, 16-bit time slots. Each frame

is subdivided into time slots consisting of 16 BCLKs per time slot. In each frame, two time slots are reserved

for control register information and eight time slots are reserved for codec data. The remaining six time slots

are unused. A pulse on FSYNC indicates the beginning of a frame.

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