TLV320AIC22CPT.B datasheet(26/56 Pages) TI2

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TLV320AIC22C

DUAL VOICE OVER INTERNET PROTOCOL (VoIP) CODEC

SPAS041B – OCTOBER 2001 – REVISED JANUARY 2003

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

address terminals

The AD1 and AD0 terminals are used to define the address of the codec in the I2C mode and for the serial

interface (see the register programming using the I2C bus section for a detailed description of the I2C mode).

For the serial interface, the address determines the time slot used by a certain codec. Provisions are made to

support up to four TLV320AIC22Cs connected to a single DSP. With four TLV320AIC22Cs, there are eight slots

used for data.

Table 5 shows how the time slots used are related to the AD1 and AD0 address lines. Codec 1 in a

TLV320AIC22C communicates during the first assigned time slot, based on the AD0 and AD1 configuration,

while codec 2 in the same TLV320AIC22C communicates during the second assigned time slot, based on that

same AD0/AD1 configuration.

Table 5. AD0 and AD1 vs Time-Slot Assignment

TLV320AIC22C

DEVICE

AD1

AD0

TIME SLOT

CODEC 1

TIME SLOT

CODEC 2

This address description is used to make the codec register address map unique across the codecs. This is

explained further in the following paragraphs.

master/slave functionality

The TLV320AIC22C can be configured as a master or a slave. A particular codec is configured as the master

by tying the M/S terminal (terminal 21) high. Tying M/S low configures the device as a slave.

This functionality can be used for connecting multiple TLV320AIC22C devices to a single McBSP port (see

Figure 20). Only one device can be a master in such a system. The master device generates the FSYNC and

the BCLK signals that are used by the DSP and the remaining TLV320AIC22Cs in the system. The slave devices

input the FSYNC and BCLK signals generated by the master device.

The TLV320AIC22C also can be used as a stand-alone slave. In this configuration, there is no master

TLV320AIC22C device providing the FSYNC and BCLK signals. FSYNC and BCLK are provided by some other

device such as a DSP or ASIC.

Careful attention must be paid to the relationship between MCLK, FSYNC, and BCLK when using stand-alone

slave configurations. When operating the device as a stand-alone slave, the configurations shown in Table 6

must be met.

Table 6. Slave-Mode Clock Inputs

MCLK INPUT

FREQUENCY

(MHz)

BCLK INPUT

FREQUENCY

(MHz)

FSYNC INPUT

FREQUENCY

(kHz)

VALUE

(BITS D6–D4, DECIMAL)

24.576

2.048

24.576

4.096

32.768

2.048

32.768

4.096

All of these signals (BCLK, MCLK, and FSYNC) must be synchronous. The appropriate values for register 12,

bits D6–D4, as well as the I values for codec 1 (register 2) and codec 2 (register 7), must be loaded prior to

transmitting and receiving valid conversion data to obtain the desired sampling rate (see the channel sampling

rates section for a detailed description).

TLV320AIC22CPT.B Datasheet(PDF) 26 Page - Texas Instruments

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