DAC38RF80IAAV datasheet(48/160 Pages) TI2

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• software compensation for phase misalignment due to PCB design errors

The concepts behind the SYSREF capture scheme are illustrated in Figure 7-11.

Figure 7-11. SYSREF Capture Strategy and Phase Tolerance Windows

To understand Figure 7-11, to begin with we’ll ignore the SYSREF phase tolerance windows in the lower portion

of the figure and focus on the blue clock waveform at the top of the figure. This waveform represents the device

clock input to a particular DAC chip. The green arrows, labeled “R” and “F”, correspond to the rising and falling

edges of this clock (ignoring for the moment the additional arrows labeled “ER” and "EF”). Lower frequency

devices captured SYSREF only on the rising edge of the device clock, the new scheme samples SYSREF on

the falling edge as well, which provides more flexibility when optimizing the setup and hold time of the SYSREF

capture path. Moreover, each time a rising SYSREF edge is captured, the chip remembers the clock phase

during which the event occurred, and the system designer can later read back the phase information to observe

the SYSREF timing relative to the device clock at the internal capture point. If SYSREF transitions close to

the rising or falling clock edge sampling points the capture flop setup and hold time may not be met and the

observed phase may be unreliable and subject to meta-stability phenomenon.

To reduce the sensitivity to setup/hold/meta-stability concerns an “early” version of the device clock is generated

within the DAC and additional SYSREF samples are taken at the “early falling” and “early rising” edges of the

clock (labeled “EF” and “ER”, respectively, in Figure 7-11). The resulting set of four samples is used to narrow

down the timing of the rising SYSREF edge to one of four possible clock phases. If the rising SYSREF transition

takes place between the “EF” and “F” samples, then SYSREF is said to occur in phase θ1. Similarly, if it takes

place between the “F” and “ER” samples, then it is said to occur in phase θ2. If SYSREF transitions between

the “ER” and “R” samples, then it is said to occur in phase θ3. And, finally, if the SYSREF rising edge event

happens between the “R” and “EF” samples, then it is said to occur in phase θ4. As mentioned before, the

chip remembers all observed SYSREF phases and the user can later read them back. Since the delay between

“early” and “on time” versions of the clock is intentionally chosen to be larger than the setup/hold/meta-stability

window, at most one of the four samples can be affected even when the SYSREF transitions right at one of the

four sampling points. Thus, the uncertainty in the observed SYSREF timing is limited to adjacent phases, and

with twice as many sampling phases the resolution of the timing information is improved by a factor of two.

Referring to the lower portion of Figure 7-11, the user can now see how this information regarding the observed

SYSREF phases is used to devise a reliable SYSREF capture methodology with a high degree of tolerance

to manufacturing and environmental variations in SYSREF phase. Based on the SYSREF phases observed

for a particular DAC chip during system characterization, the system designer can select one of four so-called

“phase tolerance window” options (denoted “’00”, “01”, “10”, and “11”) to maximize immunity to manufacturing

and environmental variations. For example, consider the default phase tolerance window labeled “window=00”

DAC38RF80, DAC38RF83, DAC38RF84

DAC38RF85, DAC38RF90, DAC38RF93

SLASEA3D – DECEMBER 2016 – REVISED DECEMBER 2023

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DAC38RF80IAAV Datasheet(PDF) 48 Page - Texas Instruments