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DAC38RF80IAAV Datasheet(PDF) 97 Page - Texas Instruments |
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DAC38RF80IAAV Datasheet(HTML) 97 Page - Texas Instruments |
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97 / 160 page  Table 7-69. FREQ_NCOCD Field Descriptions Bit Field Type Reset Description 47:0 FREQ_NCOCD R/W 0x0000 0000 0000 NCO frequency word for CD data path. 7.5.27 SYSREF Use for Clock Divider Register (address = 0x24) [reset = 0x0010] Figure 7-60. SYSREF Use for Clock Divider Register (SYSREF_CLKDIV) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 0 0 1 0 0 1 0 0 R/W R/W R/W R/W R/W R/W R/W R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7-70. SYSREF_CLKDIV Field Descriptions Bit Field Type Reset Description 15 Reserved R/W 0 Reserved 14:12 CDRVSER_SYSREF_DLY R/W 000 Programmable delay the SYSREF by N dacclk cycles to the CDRV_SER clock dividers. By offsetting the clock to the different multi-DUC blocks, clock mixing could potentially be reduced. 11:7 Not used R/W 00000 Not used 6:4 SYSREF_MODE R/W 001 Determines how SYSREF is used to sync the clock dividers in the CDRV_SER block. 000 = Don’t use SYSREF pulse 001 = Use all SYSREF pulses 010 = Use only the next SYSREF pulse 011 = Skip one SYSREF pulse then use only the next one 100 = Skip one SYSREF pulse then use all pulses. 3:2 SYSREF_DLY R/W 00 Delays the SYSREF into the CDRV_SER capture FF through 1 of 4 choices. This allows for extra delay in case the timing of the clock or SYSREF path isn’t as good as we think. 1:0 Reserved R/W 00 Reserved www.ti.com DAC38RF80, DAC38RF83, DAC38RF84 DAC38RF85, DAC38RF90, DAC38RF93 SLASEA3D – DECEMBER 2016 – REVISED DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 97 Product Folder Links: DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 |
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