L4949EP datasheet(5/10 Pages) STMICROELECTRONICS

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With this structure very low dropout voltage at

currents up to 100mA is obtained. The dropout

operation of the standby regulator is maintained

down to 3V input supply voltage. The output volt-

age is regulated up to the transient input supply

voltage of 40V. With this feature no functional in-

terruption due to overvoltage pulses is generated.

The typical curve showing the standby output

voltage as a function of the input supply voltage is

shown in Fig. 2. The current consumption of the

device (quiescent current) is less than 300

µA.

To reduce the quiescent current peak in the un-

dervoltage region and to improve the transient re-

sponse in this region, the dropout voltage is con-

trolled, the quiescent current as a function of the

supply input voltage is shown in Fig. 3.

Preregulator

To improve the transient immunity a preregulator

stabilized the internal supply voltage to 5V. This

internal voltage is present at Pin 3 (VZ). This volt-

age should not be used as an output because the

output capability is very small (

≤10µA).

This output may be used as an option when a

better transient behaviour for supply voltages less

than 8V is required (see also application note).

In this case a capacitor (100nF - 1

µF) must be

connected between Pin 3 and GND. If this feature

is not used Pin 3 must be left open.

Reset Circuit

The block circuit diagram of the reset circuit is

shown in Fig. 4. The reset circuit supervises the

output voltage.

The reset thereshold of 4.5V is defined with the

internal reference voltage and standby output

drivider.

The reset pulse delay time tRD, is defined with the

charge time of an external capacitor CT:

tRD =

• 2V

µA

The reaction time of the reset circuit originates

from the discharge time limitation of the reset ca-

pacitor CT and is proportional to the value of CT.

The reaction time of the reset circuit increases the

noise immunity. Standby output voltage drops be-

low the reset threshold only a bit longer than the

reaction time results in a shorter reset delay time.

The nominal reset delay time will be generated for

standby output voltage drops longer than approxi-

mately 50

µs.

The typical reset output waveforms are shown in

Fig. 5.

Sense Comparator

The sense comparator compares an input signal

with an internal voltage reference of typical 1.23V.

The use of an external voltage divider makes this

comparator very flexible in the application.

It can be used to supervise the input voltage

either before or after the protection diode and to

give additional informations to the microprocessor

like low voltage warnings.

Figure 3: Quiescent Current vs. Supply Voltage

Figure 2: Output Voltage vs. Input Voltage

40V

L4949E

5/10

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