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24LC024 Datasheet(PDF) 4 Page - Microchip Technology |
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24LC024 Datasheet(HTML) 4 Page - Microchip Technology |
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4 / 41 page  24AA024/24LC024/24AA025/24LC025 DS20001210Q-page 4 2007-2022 Microchip Technology Inc. and its subsidiaries TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V Extended (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V Param. No. Symbol Characteristic Min. Max. Units Conditions 1FCLK Clock Frequency — 100 kHz 1.7V ≤ VCC <1.8V — 400 kHz 1.8V ≤ VCC ≤ 5.5V 2THIGH Clock High Time 4000 — ns 1.7V ≤ VCC <1.8V 600 — ns 1.8V ≤ VCC ≤ 5.5V 3TLOW Clock Low Time 4700 — ns 1.7V ≤ VCC < 1.8V 1300 — ns 1.8V ≤ VCC ≤ 5.5V 4TR SDA and SCL Rise Time — 1000 ns 1.7V ≤ VCC < 1.8V (Note 1) — 300 ns 1.8V ≤ VCC ≤ 5.5V (Note 1) 5TF SDA and SCL Fall Time — 1000 ns 1.7V ≤ VCC < 1.8V (Note 1) — 300 ns 1.8V ≤ VCC ≤ 5.5V (Note 1) 6THD:STA Start Condition Hold Time 4000 — ns 1.7V ≤ VCC < 1.8V 600 — ns 1.8V ≤ VCC ≤ 5.5V 7TSU:STA Start Condition Setup Time 4700 — ns 1.7V ≤ VCC < 1.8V 600 — ns 1.8V ≤ VCC ≤ 5.5V 8THD:DAT Data Input Hold Time 0 — ns (Note 2) 9TSU:DAT Data Input Setup Time 250 — ns 1.7V ≤ VCC < 1.8V 100 — ns 1.8V ≤ VCC ≤ 5.5V 10 TSU:STO Stop Condition Setup Time 4000 — ns 1.7V ≤ VCC < 1.8V 600 — ns 1.8V ≤ VCC ≤ 5.5V 11 TSU:WP WP Setup Time 4000 — ns 1.7V ≤ VCC < 1.8V 600 — ns 1.8V ≤ VCC ≤ 5.5V 12 THD:WP WP Hold Time 4700 — ns 1.7V ≤ VCC < 1.8V 600 — ns 1.8V ≤ VCC ≤ 5.5V 13 TAA Output Valid from Clock — 3500 ns 1.7V ≤ VCC < 1.8V (Note 2) — 900 ns 1.8V ≤ VCC ≤ 5.5V (Note 2) 14 TBUF Bus Free Time: Bus time must be free before a new transmission can start 4700 — ns 1.7V ≤ VCC < 1.8V 1300 — ns 1.8V ≤ VCC ≤ 5.5V 15 TSP Input Filter Spike Suppression (SDA and SCL pins) —50 ns (Note 1 and Note 3) 16 TWC Write Cycle Time (byte or page) —5 ms 17 — Endurance 1,000,000 — cycles 25°C, VCC = 5.5V, Page mode (Note 4) Note 1: Not 100% tested. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. |
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