CY28158

Rev 1.0, November 20, 2006

Page 2 of 9

Pin Definitions

Name

Pins

Description

5

Reference crystal input

6

Reference crystal feedback

CPU [0–5]

41, 42, 45, 46, 49, 50

CPU clock outputs

PCI [1–5]

11, 12, 14, 15, 18

PCI clock outputs, synchronously running at 33.33 MHz

PCI_F

9

Free running PCI clock

3V66 [0–1]

25, 26

3V66 clock outputs, running at 66.66 MHz

IOAPIC [0–2]

53, 54, 55

IOAPIC clock outputs, running at 16.67 MHz

REF [0–1]

2, 3

Reference clock outputs, 14.318 MHz

48MHZ

30

48-MHz USB clock output

CPU_STOP#

36

Active LOW input, disables CPU and 3V66 clocks when asserted

PCI_STOP#

37

Active LOW input, disables PCI clocks when asserted

PWR_DWN#

35

Active LOW input, powers down part when asserted

SPREAD#

34

Active LOW input, enables spread spectrum when asserted

SEL1

33

CPU frequency select input (See Function Table)

SEL0

32

CPU frequency select input (See Function Table)

SEL133/100#

28

CPU frequency select input (See Function Table)

GND_REF

1

3.3V Reference ground

GND_PCI

7, 8, 13, 19

3.3V PCI ground

GND_3V66

20, 21, 24

3.3V 66-MHz (AGP) ground

GND_48MHZ

29

3.3V 48-MHz (USB) ground

GND_IOAPIC

52

2.5V APIC ground

GND_CPU

40, 44, 48

2.5V CPU ground

GNDA

38

Analog ground to PLL and Core

VDD_REF

4

3.3V Reference voltage supply

VDD_PCI

10, 16, 17

3.3V PCI voltage supply

VDD_3V66

22, 23, 27

3.3V 66-MHz (AGP) voltage supply

VDD_48MHZ

31

3.3V 48-MHz (USB) voltage supply

VDD_IOAPIC

56

2.5V APIC voltage supply

VDD_CPU

43, 47, 51

2.5V CPU voltage supply

VDDA

39

Analog voltage supply to PLL and Core

Note: