LAN8818D-ISLASHKDX datasheet(42/101 Pages) MICROCHIP

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LAN8818D

DS00005832C-page 42

Note, the SoC application also supports simplified 1588 operation using only the internal PLL with no external DPLL. In

this lightweight configuration, 1588 software is still required and full 1588 accuracy is available. Recovered clock jitter

and wander performance will be significantly worse compared to having an external DPLL, and it is not possible to main-

tain separate SyncE and 1588 timing.

Any timing source including the OCXO or Synchronous Ethernet Equipment Clock (EEC) might be selected as the ref-

erence clock into the 1588 Packet-based Equipment Clock (PEC). The output of the PEC provides the 1588 reference

clock used in the Switch/SoC and PHY 1588 functions. The EEC function is related to SyncE, while to PEC function is

related to PTP/1588.

System operation requires the same Time of Day (TOD) (within acceptable accuracy tolerances) exists in the switch

and PHYs. Software is able to adjust the 1588 reference clock phase and frequency in the internal PLL or external DPLL,

as well as the 1588 TOD in each device.

The device provides four 1588 Timestamp Engine instances, operating off the following clock domains:

• RX processing functions operate on each port-specific PHY RX clock domain.

• TX processing functions operate on each port-specific PHY TX clock domain.

• Control/Status Registers operate on the System clock domain.

The device also provides one instance of 1588 common functions, operating off the following clock domains:

• 1588 LTC, PPS and Event functions operate on the 1588 clock domain

• 1588 Serial Timestamp Interface and Control/Status Registers operate on the System clock domain.

The device support two basic 1588 operating modes:

• 1588 Standalone Mode Operation, in which the full classification 1588 processing capabilities are available. This

mode is to be used where the host device is not an advanced Microchip switch or other 1588 engine capable of

operating with PCH or MCH headers.

• 1588 PCH Mode Operation, in which no classification is available and only limited 1588 processing capabilities

are used. This mode is to be used where the host device is an advanced Microchip switch (SparX-5i, etc.) or other

1588 engine capable of operating with PCH or MCH headers.

5.9.1

1588 OPERATION WITH FRAME PREEMPTION

Frame Preemption defines a method to intersperse higher-priority express traffic (also called “express frames”, “com-

plete express packets” or “express packets”) with lower-priority preemptable traffic (also called “preemptable frames”,

“fragmented preemptable packets” or “complete preemptable packets”) over a single link. Formats and terminology are

defined in IEEE 802.3-2022 Clause 99. In operation, the lower priority preemptable traffic can be interrupted by the

higher priority express traffic, sometimes resulting in fragmented preemptable traffic. This device supports the 802.3-

defined formats when frame preemption is performed by the host or link partner.

Timestamping is supported only for 1588 express frames, but works in the presence of fragmented or unfragmented

preemptable frames. Timestamping of fragmented or unfragmented 1588 preemptable frames is not supported. Any

1588 preemptable frames will be passed through the device transparently.

5.9.2

1588 STANDALONE MODE OPERATION

5.9.2.1

Standalone Mode RX

In Standalone mode RX, arriving 1588 frames are identified and parsed, and the arrival timestamp is captured and

placed into the Timestamp FIFO for use in the RX or TX frame modification block, which modifies PTP Message Time-

stamps and correctionField (CF).

To interoperate with legacy VSC 1588 PHYs using E2E TC mode, arriving 1588 frames are identified and parsed, and

the arrival timestamp is captured and placed in the PTP Message header four-byte Reserved field. The format is 30-bit

nanoseconds with the upper two Reserved bits set to zero, compatible with legacy VSC timestamping PHYs.

UDP checking and updating is as follows:

• UDP/IPv4: verify zero or valid checksum. If invalid, force FCF error. If valid, clear to zero.

• UDP/IPv6: verify non-zero (if enabled) and valid checksum. If invalid, force FCS error. If valid, update checksum

pad types (if enabled).

FCS checking and updating is as follows:

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