LAN8818D-ISLASHKDX datasheet(92/101 Pages) MICROCHIP

92 / 101 page

LAN8818D

DS00005832C-page 92

6.6.15

GPIO PTP CAPTURE TIMING

Eight GPIOs can be configured to generate PTP GPIO Capture events. This section specifies the GPIO PTP capture

timing of the device.

6.6.16

RCVRD_CLK_OUT1/2 TIMING

This section specifies the RCVRD_CLK_OUT1/2 recovered clock timing of the device.

• When based on internal recovered clocks:

- Duty Cycle: (40% minimum, 50% typical, 60% maximum)

- Jitter: < 100 ps rms

• When based on external recovered clock inputs:

- Duty Cycle: (40% minimum, 50% typical, 60% maximum)

- Jitter: < 100 ps rms

6.6.17

CK125_REF_INP/M TIMING

This section specifies the CK125_REF_INP/M reference clock timing of the device.

• Duty Cycle: (40% minimum, 50% typical, 60% maximum)

• Jitter: < 100 ps rms

• Frequency: 125 MHz ± 50 ppm

6.7

Clock Circuit

If REF_CLK_SEL1=0, XI must be driven with a nominal 25 MHz single-ended clock signal meeting the following spec-

ifications:

• Duty Cycle: (40% minimum, 50% typical, 60% maximum)

• Jitter: <100 ps rms

• Frequency: 25 MHz ± 50 ppm

TABLE 6-22:

GPIO PTP CAPTURE TIMING VALUES

Symbol

Description

Min

Typ

Max

Unit

tGPIOtoLTC

GPIO Rising or falling edge to LTC Time of Day

capture latency

12.0

—

19.0

Note:

A 125 MHz differential clock reference is recommended for best QSGMII performance. Refer to the

CK125_REF_INP/CK125_REF_INM pin definitions in Table 3-4 and the LVDS1 buffer characteristics in

Table 6-5 for additional information.

LAN8818D-I/KDX Datasheet(PDF) 92 Page - Microchip Technology

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