HT25LC512

Rev. 1.00

5

June 14, 2004

·

Status register read

¨

Status register format

Bit Sequential

0

1

2

3

4

5

6

7

Bit Data

0

0

1

1

0

0

0

1

The data in the status register will always be 8CH.

To read the status register, the bit sequence is

shown below. After the last bit of the opcode is

shifted in, the eight bits of the status register, start-

ing with the MSB (bit 7), will be shifted out on the SO

pin during the next eight clock cycles. After bit 0 of

the status register has been shifted out, the se-

quence will repeat itself (as long as CS remains low

and SCK is being toggled) starting again with bit 7.

¨

Status register read

Bit sequence is shown as follows:

Bit Sequential

0

1

2

3

4

5

6

7

Bit Data

0

0

0

0

x

1

0

1

Note: ²x² don¢t care

·

Product ID read

The RDID instruction allows the user to read the man-

ufacturer and product ID of the device. The first byte

after the instruction will be the manufacture code

(1CH= HOLTEK), followed by the device code (83H

for 512K OTP ROM).

Product ID read, bit sequence is shown as follows:

Bit Sequential

0

1

2

3

4

5

6

7

Bit Data

0

0

0

1

x

1

0

1

Note: x: don¢t care

·

HOLD

The HOLD pin is used in conjunction with the CS pin

to select the HT25LC512. When the device is se-

lected and a serial sequence is underway, HOLD can

be used to pause the serial communication with the

master device without resetting the serial sequence.

To pause, the HOLD pin must be brought low while the

SCK pin is low. To resume serial communication, the

HOLD pin is brought high while the SCK pin is low

(SCK may still toggle during HOLD). Inputs to the SI

pin will be ignored while the SO pin is in the high im-

pedance state.

Power-on State

When power is first applied to the device, the SO pin will

be in a high-impedance state, and a high-to-low transi-

tion on the CS pin will be required to start a valid instruc-

tion. The SPI mode will be automatically selected on

every falling edge of CS by sampling the inactive clock

state.

Programming the OTP ROM

Programming the OTP ROM of the HT25LC512 via the

SI (Serial Input) pin requires the following sequence. Af-

ter the CS line is pulled low to select a device, the pro-

gramming instruction is transmitted via the SI line

followed by the byte address to the program. Then the

programming data are transmitted following the ad-

dress. If only one byte is to be programmed, the CS line

should be driven high after one byte data has been

transmitted. The programming instruction can be con-

tinued since the byte address is automatically incre-

mented and data will continue to be shifted in. When the

highest address is reached, the address counter will roll

over to the lowest address allowing the entire memory to

be programmed in one continuous programming in-

struction.

Programming the OTP ROM, bit sequence is shown as follows:

Bit Sequential

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Bit Data

1

0

0

1

1

0

0

1

A23 A22 A21 A20 A19 A18 A17 A16

Bit Sequential

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Bit Data

A15 A14 A13 A12 A11 A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0