CY22701FSXCT datasheet(7/15 Pages) CYPRESS

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PRELIMINARY

CY22701

Document #: 38-07698 Rev. *B

Page 7 of 15

Clock Output Settings

CLKSRC - Clock Output Crosspoint Switch Matrix

[45H(7..0)]

Both clock output can be defined to come from one of seven

unique frequency sources. The CLKSRC(2..0) crosspoint

switch matrix defines which source is attached to each

individual clock output. CLKSRC(2..0) is set in Registers 45H.

When DIV1N is divisible by 4, then CLKSRC(0,1,0) is

guaranteed

rising

edge

phase-aligned

with

CLKSRC(0,0,1). When DIV1N is 6, then CLKSRC(0,1,1) is

guaranteed

rising

edge

phase-aligned

with

CLKSRC(0,0,1).

When DIV2N is divisible by 4, then CLKSRC(1,0,1) is

guaranteed

rising

edge

phase-aligned

with

CLKSRC(1,0,0). When DIV2N is divisible by 8, then

CLKSRC(1,1,0) is guaranteed to be rising edge phase-aligned

with CLKSRC(1,0,0).

CLKOE - Clock Output Enable Control [09H(7..0)]

Each clock output has its own output enable, CLKOE,

controlled by register 09H(7..0). To enable an output, set the

corresponding CLKOE bit to 1. CLKOE settings are in

Table 13.

Test, Reserved, and Blank Registers

Writing to any of the following registers will cause the part to

exhibit abnormal behavior:

[00H to 08H] – Reserved

[0AH to 0BH] – Reserved

[0DH to 10H] –Reserved

[14H to 3FH] –Reserved

[43H to 44H] –Reserved

[48H to FFH] –Reserved

[46H] –Reserved

Table 11.Clock Output Settings – Clock Source CLKSRC[2:0]

CLKSRC2

CLKSRC1

CLKSRC0

Definition and Notes

Reference Input

DIV1CLK/DIV1N. DIV1N is defined by register [OCH]. Allowable values for DIV1N are

4 to 127. If Divider Bank 1 is not being used, set DIV1N to 8

DIV1CLK/2. Fixed /2 divider option. If this option is used, DIV1N must be divisible by 4.

DIV1CLK/3. Fixed /3 divider option. If this option is used, set DIV1N to 6.

DIV2CLK/DIV2N. DIV2N is defined by Register [47H]. Allowable values for DIV2N are

4 to 127. If Divider Bank 2 is not being used, set DIV2N to 8.

DIV2CLK/2. Fixed /2 divider option. If this option is used, DIV2N must be divisible by 4.

DIV2CLK/4. Fixed /4 divider option. If this option is used, DIV2N must be divisible by 8.

Reserved – Do not use

Table 12.CLKSRC Registers

Address

D7D6D5

D4D3D2D1

45H

CLKSRC2

for CLK1

CLKSRC1

for CLK1

CLKSRC0

for CLK1

CLKSRC2

for CLK2

CLKSRC1

for CLK2

CLKSRC0

for CLK2

Table 13.CLKOE Bit Setting

Address

D5D4

D2D1

09H

CLKOE for

CLK2

CLKOE for

CLK1

000

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