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41
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
Hardware Interface:
AD9220 data sheet
A/D
16
Analogue
In
(Chan2)
CLK
/XAOE
/XCE3
XD[0..15]
A/D
16
Analogue
In
(Chan1)
CLK
XD[16..31]
Analogue
Buffering
Latch
Latch
/OE
/OE
CLK
CLK
XTOUT0
16
16
EMIF CASE STUDY: AD9220 ADC
42
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
Both ADCs and DACs are
mapped to the same address
space (CE3 = 0xB000 0000).
/CE3
/CE3
00
00
11
/XAOE
/XAOE
00
11
xx
/XAWE
/XAWE
11
00
xx
/OE
/OE
00
11
11
DAC_CLK
DAC_CLK
11
00
11
/XAOE activates the latched A/D
output only during the read sequence
EMIF CASE STUDY: Sharing the bus
A/D
16
CLK
/XAOE
/XCE3
XD[0..15]
A/D
16
CLK
XD[16..31]
Latch
Latch
/OE
/OE
CLK
CLK
XTOUT0
16
16
D/A
16
CLK
/XAWE
/XCE3
XD[0..15]
D/A
16
CLK
XD[16..31]