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77
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
EMIF Case Study
PIPELINED SYNCHRONOUS SRAMs
SA0,SA1,SA
DQ[31:0]
CLK
ADV
MODE
ADSP
ADSC
BW[3:0]
BWE
GW
CE
CE2
CE2
OE
Address bus
SA0, SA1, SA
Data bus
DQ[31:0]
Burst control
#ADSP, #ADSC
#ADV, MODE
Write control
#BW[3:0], #BWE
#GW
Chip enable
/CE, CE2, /CE2
Output enable
/OE
CLK.
FEATURES:
Burst access.
One cycle Deselect for READ access.
MT58128L32P1
128Kx32 225 MHz
78
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
EMIF Case Study
It allows the automatic generation of the next address.
Linear or interleaved increment.
It automatically rolls over to 00 from 11.
if address 0111b were issued in burst mode, the subsequent
access would be to 0100b. => Error!
PIPELINED SYNCRONOUS SRAM: BURST MODE
Address
Clk
2-bit Counter
Address
Latch
ADV
Mode
Upper
Address
bits
Lower
2 Address
bits
2
2
A0
A1
CLK
=
First
Address
Second
Address
Third
Address
Fourth
Address
ADV=0
CLK
=
ADV=0
CLK
=
ADV=0
CLK
=
PIPELINED SYNCHRONOUS SRAMs
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