ST7FLCD1 datasheet(57/95 Pages) STMICROELECTRONICS

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ST7FLCD1

I²C Single-Master Bus Interface

Bit 1 = STOP Generation of a Stop condition.

This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled

(PE = 0) or when the Stop condition is sent. In Master mode only:

No stop generation

Stop generation after the current byte transfer or after the current Start condition is sent.

Bit 0 = ITE Interrupt enable.

This bit is set and cleared by software and cleared by hardware when the interface is disabled (PE

= 0).

Interrupt disabled

Interrupt enabled

I²C STATUS REGISTER (I2CSR)

Read Only

Reset Value: 0000 0000 (00h)

Bit 7 = EVF Event flag.

This bit is set by hardware as soon as an event occurs. It is cleared by software by reading the SR

cleared by hardware when the interface is disabled (PE = 0).

No event

One of the following events has occurred:

BTF = 1 (Byte received or transmitted)

SB = 1 (Start condition generated)

AF = 1 (No acknowledge received after byte transmission if ACK = 1)

Address byte successfully transmitted.

Bit 6 = AF Acknowledge Failure.

This bit is set by hardware when no acknowledge is returned. An interrupt is generated if ITE = 1.

It is cleared by software by reading the SR register or by hardware when the interface is disabled

(PE = 0).

The SCL line is not held low when AF = 1.

No acknowledge failure

Acknowledge failure

Bit 5 = TRA Transmitter/Receiver.

When BTF is set, TRA = 1 if a data byte has been transmitted. It is cleared automatically when BTF

is cleared. It is also cleared by hardware when the interface is disabled (PE = 0).

Data byte received (if BTF = 1)

Data byte transmitted

Bit 4 = Reserved. Forced to 0 by hardware.

Bit 3 = BTF Byte transfer finished.

This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt

765

432

EVF

TRA

BTF

M/IDL

ST7FLCD1 Datasheet(PDF) 57 Page - STMicroelectronics

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