LIS3LV02DL datasheet(23/48 Pages) STMICROELECTRONICS

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LIS3LV02DL

Digital interfaces

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5.1.1

I2C operation

The transaction on the bus is started through a START (ST) signal. A START condition is

defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After

this has been transmitted by the Master, the bus is considered busy. The next byte of data

transmitted after the start condition contains the address of the slave in the first 7 bits and

the eighth bit tells whether the Master is receiving data from the slave or transmitting data to

the slave. When an address is sent, each device in the system compares the first seven bits

after a start condition with its address. If they match, the device considers itself addressed

by the Master. The Slave ADdress (SAD) associated to the LIS3LV02DL is 0011101b.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line

during the acknowledge pulse. The receiver must then pull the data line LOW so that it

remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which

has been addressed is obliged to generate an acknowledge after each byte of data

received.

The I2C embedded inside the LIS3LV02DL behaves like a slave device and the following

protocol must be adhered to. After the start condition (ST) a salve address is sent, once a

slave acknowledge (SAK) has been returned, a 8-bit sub-address will be transmitted: the 7

LSb represent the actual register address while the MSB enables address auto increment. If

the MSb of the SUB field is 1, the SUB (register address) will be automatically incremented

to allow multiple data read/write.

The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated

START (SR) condition will have to be issued after the two sub-address bytes; if the bit is ‘0’

(Write) the Master will transmit to the slave with direction unchanged.

Table 11.

Transfer when master is writing one byte to slave

Master

SAD + W

SUB

DATA

Slave

SAK

Table 12.

Transfer when master is writing multiple bytes to slave

Master

SAD + W

SUB

DATA

Slave

SAK

Table 13.

Transfer when master is receiving (reading) one byte of data from slave

Master

SAD + W

SUB

SAD + R

NMAK

Slave

SAK

DATA

Table 14.

Transfer when master is receiving (reading) multiple bytes of data from slave

Master

ST SAD+W

SUB

SR SAD+R

MAK

NMAK

Slave

SAK

DATA

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