AT45DQ321 datasheet(39/80 Pages) RENESAS

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DS-AT45DQ321-031 Rev. H

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AT45DQ321 Datasheet

or program a protected region or a locked down sector or an attempt to erase or program a suspended sector. The

EPE bit is updated after every erase and program operation.

10.4.7

SLE Bit

The SLE bit indicates whether or not the Sector Lockdown command is enabled or disabled. If the SLE bit is a

Logic 1, then the Sector Lockdown command is still enabled and sectors can be locked down. If the SLE bit is a

Logic 0, then the Sector Lockdown command has been disabled and no further sectors can be locked down.

10.4.8

PS2 Bit

The PS2 bit indicates if a program operation has been suspended while using Buffer 2. If the PS2 bit is a Logic 1,

then a program operation has been suspended while Buffer 2 was being used, and any command attempts that

can modify the contents of Buffer 2 are ignored.

10.4.9

PS1 Bit

The PS1 bit indicates if a program operation has been suspended while using Buffer 1. If the PS1 bit is a Logic 1,

then a program operation has been suspended while Buffer 1 was being used, and any command attempts that

can modify the contents of Buffer 1 are ignored.

10.4.10 ES Bit

The ES bit indicates whether or not an erase has been suspended. If the ES bit is a Logic 1, then an erase

operation (page, block, sector, or chip) has been suspended.

10.5 Read Configuration Register

The non-volatile Configuration Register can be used to determine if the Quad-input Buffer 1 or 2 Write and

Quad-output Read Array commands have been enabled. Unlike the Status Register, the Configuration Register

can only be read when the device is in an idle state (when the RDY/ BUSY bit of the Status Register indicates that

the device is in a ready state).

To read the Configuration Register, the CS pin must first be asserted and the opcode of 3Fh must be clocked into

the device. After the opcode has been clocked in, the device begins outputting one byte of Configuration Register

data on the SO pin during subsequent clock cycles. The data being output are a repeating byte as long as the CS

pin remains asserted and the clock pin is being pulsed.

At clock frequencies above fSCK, the first byte of data output is not valid. Thus, if operating at clock frequencies

above fSCK, at least two bytes of data must be clocked out from the device in order to determine the correct value

of the Configuration Register.

Deasserting the CS pin terminates the Read Configuration Register operation and put the SO pin into a

high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be

read.

The Configuration Register is a non-volatile register; thus, the contents of the Configuration Register are not

affected by power cycles or power-on reset operations.

Table 22. Configuration Register Format

1. Only bit seven of the Configuration Register is modified when using the Quad Enable/Disable commands.

Bit

Name

Type

Description

Quad Enable

R/W

Quad-input/output commands and operation disabled.

Quad-input/output commands and operation enabled. (WP and

RESET disabled).

6:4

RES

Reserved for Future Use

Reserved for future use.

RES

Reserved for Future Use

Reserved for future use.

2:0

RES

Reserved for Future Use

Reserved for future use.

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