APEX20KC datasheet(8/90 Pages) ALTERA

8 / 90 page

Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

The ESB can implement a variety of memory functions, including CAM,

RAM, dual-port RAM, ROM, and FIFO functions. Embedding the

memory directly into the die improves performance and reduces die area

compared to distributed-RAM implementations. Moreover, the

abundance of cascadable ESBs allows APEX 20KC devices to implement

multiple wide memory blocks for high-density designs. The ESB’s high

speed ensures it can implement small memory blocks without any speed

penalty. Additionally, designers can use the ESBs to create as many

different-sized memory blocks as the system requires. Figure 1 shows an

overview of the APEX 20KC device.

Figure 1. APEX 20KC Device Block Diagram

APEX 20KC devices provide four dedicated clock pins and four dedicated

input pins that drive register control inputs. These signals ensure efficient

distribution of high-speed, low-skew control signals, which use dedicated

routing channels to provide short delays and low skews. Four of the

dedicated inputs drive four global signals. These four global signals can

also be driven by internal logic, providing an ideal solution for a clock

divider or internally generated asynchronous clear signals with high

fan-out. The dedicated clock pins featured on the APEX 20KC devices can

also feed logic. The devices also feature ClockLock and ClockBoost clock

management circuitry.

LUT

Memory

IOE

LUT

Memory

IOE

Product Term

LUT

Memory

IOE

Product Term

FastTrack

Interconnect

Clock Management Circuitry

IOEs support

PCI, GTL+,

SSTL-3, LVDS,

and other

standards.

ClockLock

Four-input LUT

for data path and

DSP functions.

Product-term

integration for

high-speed

control logic and

state machines.

Flexible integration

of embedded

memory, including

CAM, RAM,

ROM, FIFO, and

other memory

functions.

APEX20KC Datasheet(PDF) 8 Page - Altera Corporation

APEX20KC Datasheet(HTML) 8 Page - Altera Corporation

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