APEX20KC datasheet(2/90 Pages) ALTERA

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Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

...and More

Features

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Low-power operation design

–

1.8-V supply voltage (see Table 2)

–

Copper interconnect reduces power consumption

–MultiVoltTM I/O support for 1.8-V, 2.5-V, and 3.3-V interfaces

–

ESBs offering programmable power-saving mode

■

Flexible clock management circuitry with up to four phase-locked

loops (PLLs)

–

Built-in low-skew clock tree

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Up to eight global clock signals

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ClockLockTM feature reducing clock delay and skew

–ClockBoostTM feature providing clock multiplication and

division

–

ClockShiftTM feature providing programmable clock phase and

delay shifting

■

Powerful I/O features

–

Compliant with peripheral component interconnect Special

Interest Group (PCI SIG) PCI Local Bus Specification,

Revision 2.2

for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits

–

Support for high-speed external memories, including DDR

synchronous dynamic RAM (SDRAM) and ZBT static RAM

(SRAM)

–

16 input and 16 output LVDS channels at 840 megabits per

second (Mbps)

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Direct connection from I/O pins to local interconnect providing

fast tCO and tSU times for complex logic

–

MultiVolt I/O support for 1.8-V, 2.5-V, and 3.3-V interfaces

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Programmable clamp to VCCIO

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Individual tri-state output enable control for each pin

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Programmable output slew-rate control to reduce switching

noise

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Support for advanced I/O standards, including low-voltage

differential signaling (LVDS), LVPECL, PCI-X, AGP, CTT,

SSTL-3 and SSTL-2, GTL+, and HSTL Class I

–

Supports hot-socketing operation

–

Pull-up on I/O pins before and during configuration

Note to Table 2:

(1)

APEX 20KC devices can be 5.0-V tolerant by using an external resistor.

Table 2. APEX 20KC Supply Voltages

Feature

Voltage

Internal supply voltage (VCCINT)

1.8 V

MultiVolt I/O interface voltage levels (VCCIO) 1.8 V, 2.5 V, 3.3 V, 5.0 V (1)

APEX20KC Datasheet(PDF) 2 Page - Altera Corporation

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