C8051F310 datasheet(99/228 Pages) SILABS

99 / 228 page

Rev. 1.7

C8051F310/1/2/3/4/5/6/7

SFR Definition 8.9. EIE1: Extended Interrupt Enable 1

Bit7:

ET3: Enable Timer 3 Interrupt.

This bit sets the masking of the Timer 3 interrupt.

0: Disable Timer 3 interrupts.

1: Enable interrupt requests generated by the TF3L or TF3H flags.

Bit6:

ECP1: Enable Comparator1 (CP1) Interrupt.

This bit sets the masking of the CP1 interrupt.

0: Disable CP1 interrupts.

1: Enable interrupt requests generated by the CP1RIF or CP1FIF flags.

Bit5:

ECP0: Enable Comparator0 (CP0) Interrupt.

This bit sets the masking of the CP0 interrupt.

0: Disable CP0 interrupts.

1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags.

Bit4:

EPCA0: Enable Programmable Counter Array (PCA0) Interrupt.

This bit sets the masking of the PCA0 interrupts.

0: Disable all PCA0 interrupts.

1: Enable interrupt requests generated by PCA0.

Bit3:

EADC0: Enable ADC0 Conversion Complete Interrupt.

This bit sets the masking of the ADC0 Conversion Complete interrupt.

0: Disable ADC0 Conversion Complete interrupt.

1: Enable interrupt requests generated by the AD0INT flag.

Bit2:

EWADC0: Enable Window Comparison ADC0 Interrupt.

This bit sets the masking of ADC0 Window Comparison interrupt.

0: Disable ADC0 Window Comparison interrupt.

1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).

Bit1:

RESERVED. Read = 0. Must Write 0.

Bit0:

ESMB0: Enable SMBus (SMB0) Interrupt.

This bit sets the masking of the SMB0 interrupt.

0: Disable all SMB0 interrupts.

1: Enable interrupt requests generated by SMB0.

R/W

Reset Value

ET3

ECP1

ECP0

EPCA0

EADC0

EWADC0 Reserved

ESMB0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xE6

C8051F310 Datasheet(PDF) 99 Page - Silicon Laboratories

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