DA7218 datasheet(86/154 Pages) RENESAS

86 / 154 page

Ultra-Low Power Stereo Codec

R32DS0004EE0370 Revision 3.7

Aug 9, 2024

CFR0011-120-00

Page 86

Bit

Mode

Symbol

Description

Reset

R/W

dai_clk_pol

DAI bit clock polarity control

0 = Normal polarity

1 = Inverted polarity

0x0

1:0

R/W

dai_bclks_per_wclk

Number of BCLK cycles per WCLK period in DAI master

mode

00 = 32 BCLK cycles per WCLK

01 = 64 BCLK cycles per WCLK

10 = 128 BCLK cycles per WCLK

11 = 256 BCLK cycles per WCLK

0x1

Table 105: Register map dgs_cor_00 page 0

Address

Name

0x00000054

DGS_TRIGGER

Reserved

dgs_trigger_lvl

0x00000055

DGS_ENABLE

Reserved

dgs_enable

0x00000056

DGS_RISE_FALL

Reserved

dgs_fall_coeff

Reserved

dgs_rise_coeff

0x00000057

DGS_SYNC_DELAY

dgs_sync_delay

0x00000058

DGS_SYNC_DELAY2

dgs_sync_delay2

0x00000059

DGS_SYNC_DELAY3

Reserved

dgs_sync_delay3

0x0000005A

DGS_LEVELS

dgs_signal_lvl

Reserved

dgs_anticlip_lvl

0x0000005B

DGS_GAIN_CTRL

Reserved

dgs_subr_en

dgs_ramp_en

dgs_steps

Table 106: DGS_TRIGGER (Page 0: 0x00000054)

Bit

Mode

Symbol

Description

Reset

5:0

R/W

dgs_trigger_lvl

DAC Gain Swap (DGS) input-amplitude trigger level

control. This sets the volume level at which all DGS

steps are applied.

0x00 = 0 dB

0x01 = -1.5 dB

0x02 = -3 dB

continuing in -1.5 dB steps through...

0x24 = -54 dB (default)

to...

0x3e = -93 dB

0x3f = -94.5 dB

0x24

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