TMS320VC5502 datasheet(88/190 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166J – APRIL 2001 – REVISED AUGUST 2006

3.12.2.2 Parallel GPIO Direction Register 0 (PGPIODIR0)

IO15DIR

IO14DIR

IO13DIR

IO12DIR

IO11DIR

IO10DIR

IO9DIR

IO8DIR

R/W, 0

IO7DIR

IO6DIR

IO5DIR

IO4DIR

IO3DIR

IO2DIR

IO1DIR

IO0DIR

R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3-35. Parallel GPIO Direction Register 0 Layout (0x4401)

Table 3-38. Parallel GPIO Direction Register 0 Bit Field Description

(1)

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

IOxDIR

15-0

R/W

0000000000000000

Data direction bits specify if corresponding bits in the data

registers specify an output value or an input value. See

Table 3-36, TMS320VC5502 PGPIO Cross-Reference to

determine which device pins correspond to the PGPIO pins.

•

IOxDIR = 0:

Corresponding bit in the data register specifies the value

read on the PGPIOx pin (input). When IOxDIR = 0, IOxEN

must also be cleared to 0.

•

IOxDIR = 1:

Corresponding bit in the data register specifies the value

driven on the PGPIOx pin (output). When IOxDIR = 1, IOxEN

must also be set to 1.

(1)

x = value from 0 to 15

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