TMS320VC5502 datasheet(94/190 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166J – APRIL 2001 – REVISED AUGUST 2006

3.12.2.8 Parallel GPIO Direction Register 2 (PGPIODIR2)

Reserved

IO45DIR

IO44DIR

IO43DIR

IO42DIR

IO41DIR

IO40DIR

R/W, 00

R/W, 0

IO39DIR

IO38DIR

IO37DIR

IO36DIR

IO35DIR

IO34DIR

IO33DIR

IO32DIR

R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3-41. Parallel GPIO Direction Register 2 Layout (0x4407)

Table 3-44. Parallel GPIO Direction Register 2 Bit Field Description

(1)

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

Reserved

15-14

R/W

Reserved

IOxDIR

13-0

R/W

00000000000000 Data direction bits specify if corresponding bits in the data registers

specify an output value or an input value. See Table 3-36,

TMS320VC5502 PGPIO Cross-Reference to determine which device

pins correspond to the PGPIO pins.

•

IOxDIR = 0:

Corresponding bit in the data register specifies the value read on

the PGPIOx pin (input). When IOxDIR = 0, IOxEN must also be

cleared to 0.

•

IOxDIR = 1:

Corresponding bit in the data register specifies the value driven

on the PGPIOx pin (output). When IOxDIR = 1, IOxEN must also

be set to 1.

(1)

x = value from 32 to 45

Functional Overview

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