R5F5651CDDFB datasheet(94/188 Pages) RENESAS

94 / 188 page

R01DS0276EJ0240 Rev.2.40

Page 94 of 188

Oct 31, 2023

RX65N Group, RX651 Group

2. Electrical Characteristics

registers A to D.

Note 5. When the peripheral module clock is stopped, the settings of the clock frequency are as follows:

ICLK = 120 MHz and PCLKA = PCLKB = PCLKC = PCLKD = FCLK = BCLK = BCLK pin = 3.75 MHz (divided by 64).

Note 6. When the low power consumption function is disabled, the DEEPCUT[1:0] bits are set to 01b.

Note 7. When the low power consumption function is enabled, the DEEPCUT[1:0] bits are set to 11b.

Note 8. Reference value

Note 1. Supply current values are measured when all output pins are unloaded and all input pull-up resistors are disabled.

Note 2. Peripheral module clocks are supplied.

Note 3. ICC depends on the f (ICLK) as follows (when ICLK/PCLKA : PCLKB/PCLKC/PCLKD : BCLK : BCLK pin = 2 : 1 : 2 : 1 and

Table 2.7

DC Characteristics (3) (Products with at least 1.5 Mbytes of code flash memory)

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

Ta = Topr

Item

Symbol

D version

G version

Unit

Test Conditions

Typ. Max. Typ. Max.

Supply

current*1

Full operation*2

ICC*3

—

ICLK = 120 MHz,

PCLKA = 120 MHz,

PCLKB = 60 MHz,

PCLKC = 60 MHz,

PCLKD = 60 MHz,

FCLK = 60 MHz,

BCLK = 120 MHz,

BCLK pin = 60 MHz

Normal

operation

Peripheral module clocks are supplied*4

—

Peripheral module clocks are stopped

*4, *5

—

Core

Mark

Peripheral module clocks are stopped

*4, *5

—

Sleep mode: Peripheral module clocks are supplied

All module clock stop mode (reference value)

Increased by BGO

operation

Reading from the code flash

memory while the data flash

memory is being programmed

6—6—

Reading from the code flash

memory while the code flash

memory is being programmed

7—7—

Increased by Trusted Secure IP operation

—

Low-speed operating mode 1: Peripheral module clocks

are stopped*4

1.6

—

1.6

—

All clocks 1 MHz

Low-speed operating mode 2: Peripheral module clocks

are stopped*4

1.6

—

1.6

—

All clocks 32.768

kHz

Software standby mode

1.6

22.4

Power is supplied to the standby RAM and USB

resume detecting unit (USB0 only)

15.5

µA

Power is not

supplied to the

standby RAM and

USB resume

detecting unit

(USB0 only)

Low power consumption

function of the power-on reset

circuit is disabled*6

11.5

Low power consumption

function of the power-on reset

circuit is enabled*7

4.9324.9

Increase current

by operating RTC

When a low CL crystal is in

use

1—1—

When a standard CL crystal is

in use

2—2—

When the RTC is

operating while VCC is

not supplied (Only the

RTC and sub-clock

oscillator operate with

the battery backup

function)

When a low CL crystal is in

use

0.9

—

0.9

—

VBATT = 2.0 V,

VCC = 0 V

1.6

—

1.6

—

VBATT = 3.3 V,

VCC = 0 V

When a standard CL crystal is

in use

1.6

—

1.6

—

VBATT = 1.62 V,

VCC = 0 V

1.7

—

1.7

—

VBATT = 2.0 V,

VCC = 0 V

3.3

—

3.3

—

VBATT = 3.3 V,

VCC = 0 V

Inrush current on

release from deep

software standby mode

Inrush current*9

IRUSH

—130

Total inrush current*9

ERUSH

—1.0

µC

R5F5651CDDFB Datasheet(PDF) 94 Page - Renesas Technology Corp

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