MB91F313 datasheet(62/71 Pages) FUJITSU

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MB91313 Series

(12) I2C timing

• When operating in master mode

(VDDE

= 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = −40 °C to + 85 °C)

*1 : For use at over 100 kHz, set the resource clock to 6 MHz or higher.

*2 : R and C represent the pull-up resistance and load capacitance of the SCL and SDA output lines, respectively.

*3 : M

= Resource clock cycle (ns)

*4 : A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device

satisfies the requirement of “tSUDAT

≥ 250 ns”.

When a device does not extend the “L” period of the SCL signal, the next data must be output to the SDA line

within 1250 ns (maximum SDA/SCL rise time

+ tSUDAT) from when the SCL line is released.

Parameter

Symbol Conditions

Typical mode

High-speed

mode*1

Unit

Remarks

Min

Max

Min

Max

SCL clock frequency

fSCL

= 1 kΩ,

= 50 pF*2

100

400

kHz

“L” period of SCL clock

tLOW

4.7

⎯

1.3

⎯µs

“H” period of SCL clock

tHIGH

4.0

⎯

0.6

⎯µs

Bus free time between

“STOP condition” and

“START condition”

tBUS

4.7

⎯

1.3

⎯µs

SCL

↓ → SDA

output delay time

tDLDAT

⎯

× M*3

⎯

× M*3

“Repeated START condition”

setup time SCL

↑ → SDA ↓

tSUSTA

4.7

⎯

0.6

⎯µs

“Repeated START condition”

hold time SDA

↓ → SCL ↓

tHDSTA

4.0

⎯

0.6

⎯µs

The first clock

pulse is generat-

ed after this.

“STOP condition” setup time

SCL

↑ → SDA ↑

tSUSTO

4.0

⎯

0.6

⎯µs

SDA data input hold time

(vs. SCL

↓)

tHDDAT

× M*3

⎯

× M*3

⎯µs

SDA data input setup time

(vs. SCL

↑)

tSUDAT

250

⎯

100*4

⎯

MB91F313 Datasheet(PDF) 62 Page - fujitsu semiconductor

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