RIVA128 datasheet(2/77 Pages) STMICROELECTRONICS

2 / 77 page

RIVA 128

128-BIT 3D MULTIMEDIA ACCELERATOR

TABLE OF CONTENTS

2/77

REVISION HISTORY ......................................................................................................................

RIVA 128 300PBGA DEVICE PINOUT ..........................................................................................

PIN DESCRIPTIONS ......................................................................................................................

2.1

ACCELERATED GRAPHICS PORT (AGP) INTERFACE .....................................................

2.2

PCI 2.1 LOCAL BUS INTERFACE ........................................................................................

2.3

SGRAM FRAMEBUFFER INTERFACE ................................................................................

2.4

VIDEO PORT.........................................................................................................................

2.5

DEVICE ENABLE SIGNALS..................................................................................................

2.6

DISPLAY INTERFACE ..........................................................................................................

2.7

VIDEO DAC AND PLL ANALOG SIGNALS ..........................................................................

2.8

POWER SUPPLY ..................................................................................................................

2.9

TEST......................................................................................................................................

OVERVIEW OF THE RIVA 128 ......................................................................................................

3.1

BALANCED PC SYSTEM......................................................................................................

3.2

HOST INTERFACE ...............................................................................................................11

3.3

2D ACCELERATION .............................................................................................................

3.4

3D ENGINE ...........................................................................................................................

3.5

VIDEO PROCESSOR............................................................................................................

3.6

VIDEO PORT.........................................................................................................................

3.7

DIRECT RGB OUTPUT TO LOW COST PAL/NTSC ENCODER .........................................

3.8

SUPPORT FOR STANDARDS..............................................................................................

3.9

RESOLUTIONS SUPPORTED..............................................................................................

3.10 CUSTOMER EVALUATION KIT............................................................................................

3.11 TURNKEY MANUFACTURING PACKAGE...........................................................................

ACCELERATED GRAPHICS PORT (AGP) INTERFACE .............................................................

4.1

RIVA 128 AGP INTERFACE .................................................................................................

4.2

AGP BUS TRANSACTIONS..................................................................................................

PCI 2.1 LOCAL BUS INTERFACE.................................................................................................

5.1

RIVA 128 PCI INTERFACE ...................................................................................................

5.2

PCI TIMING SPECIFICATION...............................................................................................

SGRAM FRAMEBUFFER INTERFACE.........................................................................................

6.1

SGRAM INITIALIZATION ......................................................................................................

6.2

SGRAM MODE REGISTER ..................................................................................................

6.3

LAYOUT OF FRAMEBUFFER CLOCK SIGNALS ................................................................

6.4

SGRAM INTERFACE TIMING SPECIFICATION ..................................................................

VIDEO PLAYBACK ARCHITECTURE...........................................................................................

7.1

VIDEO SCALER PIPELINE ...................................................................................................

VIDEO PORT ..................................................................................................................................

8.1

VIDEO INTERFACE PORT FEATURES ...............................................................................

8.2

BI-DIRECTIONAL MEDIA PORT POLLING COMMANDS USING MPC ..............................

8.3

TIMING DIAGRAMS ..............................................................................................................42

8.4

656 MASTER MODE .............................................................................................................

8.5

VBI HANDLING IN THE VIDEO PORT .................................................................................

8.6

SCALING IN THE VIDEO PORT ...........................................................................................

BOOT ROM INTERFACE...............................................................................................................

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