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PSD934210MIT Datasheet(PDF) 51 Page - STMicroelectronics |
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PSD934210MIT Datasheet(HTML) 51 Page - STMicroelectronics |
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51 / 89 page ![]() 51/89 PSD834F2V Figure 25. Port A and Port B Structure Ports A and B – Functionality and Structure Ports A and B have similar functionality and struc- ture, as shown in Figure 25. The two ports can be configured to perform one or more of the following functions: s MCU I/O Mode s CPLD Output – Macrocells McellAB7-McellAB0 can be connected to Port A or Port B. McellBC7- McellBC0 can be connected to Port B or Port C. s CPLD Input – Via the Input Macrocells (IMC). s Latched Address output – Provide latched address output as per Table 20. s Address In – Additional high address inputs using the Input Macrocells (IMC). s Open Drain/Slew Rate – pins PA3-PA0 and PB3-PB0 can be configured to fast slew rate, pins PA7-PA4 and PB7-PB4 can be configured to Open Drain Mode. s Data Port – Port A to D7-D0 for 8 bit non- multiplexed bus s Multiplexed Address/Data port for certain types of MCU bus interfaces. s Peripheral Mode – Port A only DATA OUT REG. DQ D G Q DQ DQ WR WR WR ADDRESS MACROCELL OUTPUTS ENABLE PRODUCT TERM (.OE) ALE READ MUX P D B CPLD - INPUT CONTROL REG. DIR REG. INPUT MACROCELL ENABLE OUT DATA IN OUTPUT SELECT OUTPUT MUX PORT A OR B PIN DATA OUT ADDRESS A[ 7:0] OR A[15:8] AI02887 |
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