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© 2015-2024 Renesas Electronics Corporation

November 7, 2024

830S21I Datasheet

Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL

and other differential signals. Both VSWING and VOH must meet the

VPP and VCMR input requirements. Figures 2A to 2F show interface

examples for the HiPerClockS CLK/nCLK input driven by the most

common driver types. The input interfaces suggested here are

examples only. Please consult with the vendor of the driver

component to confirm the driver termination requirements. For

example, in Figure 2A, the input termination applies for IDT

HiPerClockS open emitter LVHSTL drivers. If you are using an

LVHSTL driver from another vendor, use their termination

recommendation.

Figure 2A. HiPerClockS CLK/nCLK Input

Driven by an IDT Open Emitter

HiPerClockS LVHSTL Driver

Figure 2C. HiPerClockS CLK/nCLK Input

Driven by a 3.3V LVPECL Driver

Figure 2E. HiPerClockS CLK/nCLK Input

Driven by a 3.3V HCSL Driver

Figure 2B. HiPerClockS CLK/nCLK Input

Driven by a 3.3V LVPECL Driver

Figure 2D. HiPerClockS CLK/nCLK Input

Driven by a 3.3V LVDS Driver

Figure 2F. HiPerClockS CLK/nCLK Input

Driven by a 2.5V SSTL Driver

R1

50

R2

50

1.8V

Zo = 50

Zo = 50

CLK

nCLK

3.3V

LVHSTL

IDT

LVHSTL Driver

Differential

Input

HCSL

*R3

*R4

CLK

nCLK

3.3V

3.3V

Differential

Input

CLK

nCLK

Differential

Input

SSTL

2.5V

Zo = 60

Zo = 60

2.5V

3.3V

R1

120

R2

120

R3

120

R4

120