ADF4206/ADF4208

Rev. A | Page 7 of 24

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VDD1

VP1

CPRF1

DGNDRF1

RF1IN

OSCIN

OSCOUT

MUXOUT

VDD2

VP2

CPRF2

DGNDRF2

RF2IN

LE

DATA

CLK

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

ADF4206

TOP VIEW

(Not to Scale)

VDD1

CPRF1

DGNDRF1

RF1IN A

OSCIN

OSCOUT

MUXOUT

RF1IN B

AGNDRF1

VDD2

CPRF2

AGNDRF2

LE

DATA

CLK

RF2IN B

RF2IN A

DGNDRF2

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

ADF4208

TOP VIEW

(Not to Scale)

VP1

VP2

Figure 3. 16-Lead TSSOP Pin Configuration

Figure 4. 20-Lead TSSOP Pin Configuration

Table 4. Pin Function Descriptions

ADF4206

Pin No.

ADF4208

Pin No.

Mnemonic

Description

1

1

VDD1

Positive Power Supply for the RF1 Section. A 0.1 μF capacitor is connected between this pin

and DGNDRF1 (the RF1 ground pin). VDD1 should have a value of between 2.7 V and 5.5 V. VDD1

must have the same potential as VDD2.

2

2

VP1

Power Supply for the RF1 Charge Pump. This is greater than or equal to VDD.

3

3

CPRF1

Output from the RF1 Charge Pump. This is normally connected to a loop filter that drives the

input to an external VCO.

4

4

DGNDRF1

Ground Pin for the RF1 Digital Circuitry.

5

5

RF1IN/RF1INA

Input to the RF1 Prescaler. This low level input signal is taken from the RF1 VCO.

6

8

OSCIN

Oscillator Input. It has a VDD/2 threshold and is driven from an external CMOS or TTL logic gate.

7

9

OSCOUT

Oscillator Output.

8

10

MUXOUT

This multiplexer output allows the IF/RF lock detect, the scaled RF, or the scaled reference

frequency external access. See Figure 30.

9

11

CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is

latched into the 22-bit shift register on the CLK rising edge. This input is a high impedance

CMOS input.

10

12

DATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This

input is a high impedance CMOS input.

11

13

LE

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded

into one of the four latches, the latch being selected using the control bits.

12

16

RF2IN/RF2INA

Input to the RF2 Prescaler. This low level input signal is normally ac-coupled to the external

VCO.

13

17

DGNDRF2

Ground Pin for the RF2, Digital, Interface, and Control Circuitry.

14

18

CPRF2

Output from the RF2 Charge Pump. This is normally connected to a loop filter that drives the

input to an external VCO.

15

19

VP2

Power Supply for the RF2 Charge Pump. This is greater than or equal to VDD.

16

20

VDD2

Positive Power Supply for the RF2, Interface, and Oscillator Sections. A 0.1 μF capacitor is

connected between this pin and DGNDRF2 (the RF2 ground pin). VDD2 has a value between 2.7 V

and 5.5 V. VDD2 must have the same potential as VDD1.

N/A

6

RF1INB

Complementary Input to the RF1 Prescaler of the ADF4208. This point is decoupled to the

ground plane with a small bypass capacitor.

N/A

7

AGNDRF1

Ground Pin for the RF1 Analog Circuitry.

N/A

14

AGNDRF2

Ground Pin for the RF2 Analog Circuitry.

N/A

15

RF2INB

Complementary Input to the RF2 Prescaler. This point is decoupled to the ground plane with a

small bypass capacitor.