ADF4206 datasheet(11/24 Pages) AD

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ADF4206/ADF4208

Rev. A | Page 11 of 24

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 22. SW1 and SW2

are normally closed switches. SW3 is normally open. When

power-down is initiated, SW3 is closed and SW1 and SW2 are

opened. Typical recommended external components are shown

in Figure 22.

30pF

OSCIN

OSCOUT

TO R

COUNTER

BUFFER

POWER-DOWN

CONTROL

SW1

SW2

100kΩ

SW3

18kΩ

30pF

Figure 22. Reference Input Stage

RF INPUT STAGE

The RF input stage is shown in Figure 23. It is followed by a

2-stage limiting amplifier to generate the CML clock levels

needed for the prescaler.

RFINA

AVDD

BIAS

GENERATOR

1.6V

2kΩ

AGND

2kΩ

RFINB

Figure 23. RF Input Stage

PRESCALER

The dual modulus prescaler (P/P + 1), along with the A and

B counters, enables the large division ratio, N, to be realized

(N = BP + A). This prescaler, operating at CML levels, takes

the clock from the RF input stage and divides it down to a

manageable frequency for the CMOS A and B counters. It is

based on a synchronous 4/5 core.

The prescaler is selectable. Both RF1 and RF2 can be set to

either 32/33 or 64/65. DB20 of the AB counter latch selects the

value. See Figure 29 and Figure 31.

A AND B COUNTERS

The A and B CMOS counters combine with the dual modulus

prescaler to allow a wide ranging division ratio in the PLL

feedback counter. The devices are guaranteed to work when the

prescaler output is 200 MHz or less.

PULSE SWALLOW FUNCTION

The A and B counters, in conjunction with the dual modulus

prescaler, make it possible to generate output frequencies that

are spaced only by the reference frequency divided by R. The

equation for the VCO frequency is

fVCO = [(P × B) + A] × fREFIN/R

where:

fVCO is the output frequency of the external voltage controlled

oscillator (VCO).

P is the preset modulus of the dual modulus prescaler

(32/33, 64/65).

B is the preset divide ratio of the binary 11-bit counter

(2 to 2047).

A is the preset divide ratio of the binary 6-bit A counter

(0 to 63).

fREFIN is the output frequency of the external reference frequency

oscillator.

R is the preset divide ratio of the binary 14-bit programmable

reference counter (1 to 16,383).

R COUNTER

The 14-bit R counter allows the input reference frequency to be

divided down to produce the reference clock to the phase

frequency detector (PFD). Division ratios from 1 to 16,383 are

allowed.

PRESCALER

P/P + 1

MODULUS

CONTROL

FROM RF

INPUT STAGE

LOAD

N = BP + A

N DIVIDER

LOAD

TO PFD

11-BIT B

COUNTER

6-BIT A

COUNTER

Figure 24. A and B Counters

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