ADV7181C

Data Sheet

Rev. E | Page 16 of 20

On the ADV7181C, it is recommended to use the ADC mapping shown in Table 8.

Table 8. Recommended ADC Mapping

Mode

Required ADC Mapping

AIN Channel

Core

Configuration1

CVBS

ADC0

CVBS = A

IN1

SD

INSEL[3:0] = 0000

SDM_SEL[1:0] = 00

PRIM_MODE[3:0] = 0000

VID_STD[3:0] = 0010

YC/YC auto

Y = ADC0

Y = A

IN2

SD

INSEL[3:0] = 0000

C = ADC1

C = A

IN3

SDM_SEL[1:0] = 11

PRIM_MODE[3:0] = 0000

VID_STD[3:0] = 0010

Component YUV

Y = ADC0

Y = A

IN6

SD

INSEL[3:0] = 1001

U = ADC2

U = A

IN4

SDM_SEL[1:0] = 00

V = ADC1

V = A

IN5

PRIM_MODE[3:0] = 0000

VID_STD[3:0] = 0010

Component YUV

Y = ADC0

Y = A

IN6

CP

INSEL[3:0] = 0000

U = ADC2

U = A

IN4

SDM_SEL[1:0] = 00

V = ADC1

V = A

IN5

PRIM_MODE[3:0] = 0000

VID_STD[3:0] = 1010

SCART RGB

CBVS = ADC0

CVBS = A

IN2

SD

INSEL[3:0] = 0000

G = ADC1

G = A

IN6

SDM_SEL[1:0] = 00

B = ADC3

B = A

IN4

PRIM_MODE[3:0] = 0000

R = ADC2

R = A

IN5

VID_STD[3:0] = 0010

Graphics

G = ADC0

G = A

IN6

CP

INSEL[3:0] = 0000

RGB Mode

B = ADC2

B = A

IN4

SDM_SEL[1:0] = 00

R = ADC1

R = A

IN5

PRIM_MODE[3:0] = 0001

VID_STD[3:0] = 1100

1 Configuration to format follow-on blocks in correct format.

Table 9. Manual MUX Settings for All ADCs

ADC_SWITCH_MAN to 1

ADC0_SW_SEL[3:0]

ADC0

Connection ADC1_SW_SEL[3:0]

ADC1

Connection ADC2_SW_SEL[3:0]

ADC2

Connection ADC3_SW_SEL[3:0]

ADC3

Connection

0001

A

IN1

0001

N/A

0001

N/A

0001

N/A

0010

A

IN2

0010

N/A

0010

A

IN2

0010

N/A

0100

A

IN4

0100

A

IN4

0100

A

IN4

0100

A

IN4

0101

A

IN5

0101

A

IN5

0101

A

IN5

0101

N/A

0110

A

IN6

0110

A

IN6

0110

A

IN6

0110

N/A

1100

A

IN3

1100

A

IN3

1100

N/A

1100

N/A

The analog input muxes of the ADV7181C must be controlled

directly. This is referred to as manual input muxing. The manual

muxing is activated by setting the ADC_SWITCH_MAN bit

(see Table 9). It affects only the analog switches in front of the

ADCs. INSEL, SDM_SEL, PRIM_MODE, and VID_STD still

have to be set so that the follow-on blocks process the video

data in the correct format.

Not every input pin can be routed to any ADC. There are

restrictions in the channel routing imposed by the analog signal

routing inside the IC. See Table 9 for an overview of the routing

capabilities inside the chip. The four mux sections can be

controlled by the reserved control signal buses ADC0_SW[3:0]/

ADC1_SW[3:0]/ADC2_SW[3:0]/ADC3_SW[3:0].

Table 9 explains the ADC mapping configuration for the following:

•

ADC_SW_MAN_EN, manual input muxing enable,

IO map, Address C4[7]

•

ADC0_SW[3:0], ADC0 mux configuration, IO map,

Address C3[3:0]

•

ADC1_SW[3:0], ADC1 mux configuration, IO map,

Address C3[7:4]

•

ADC2_SW[3:0], ADC2 mux configuration, IO map,

Address C4[3:0]

•

ADC3_SW[3:0], ADC3 mux configuration, IO map,

Address F3[7:4]