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NRF52811-QCAA-R Datasheet(PDF) 163 Page - Nordic Semiconductor |
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NRF52811-QCAA-R Datasheet(HTML) 163 Page - Nordic Semiconductor |
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163 / 444 page ![]() Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field Value ID Value Description A RW UPDOWN Selects up mode or up-and-down mode for the counter Up 0 Up counter, edge-aligned PWM duty cycle UpAndDown 1 Up and down counter, center-aligned PWM duty cycle 6.12.5.15 COUNTERTOP Address offset: 0x508 Value up to which the pulse generator counter counts Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A Reset 0x000003FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 ID Access Field Value ID Value Description A RW COUNTERTOP [3..32767] Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. 6.12.5.16 PRESCALER Address offset: 0x50C Configuration for PWM_CLK Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field Value ID Value Description A RW PRESCALER Prescaler of PWM_CLK DIV_1 0 Divide by 1 (16 MHz) DIV_2 1 Divide by 2 (8 MHz) DIV_4 2 Divide by 4 (4 MHz) DIV_8 3 Divide by 8 (2 MHz) DIV_16 4 Divide by 16 (1 MHz) DIV_32 5 Divide by 32 (500 kHz) DIV_64 6 Divide by 64 (250 kHz) DIV_128 7 Divide by 128 (125 kHz) 6.12.5.17 DECODER Address offset: 0x510 Configuration of the decoder 4454_140 v1.0 163 |
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