NRF52811-QCAA-R datasheet(306/444 Pages) NORDIC

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Peripherals

DEF

CPU

Free

CPUPENDING

CPU

Ignored

Granted

Ignored

DEF

CPU

Free

DEF

SPI master can use the DEF

character to stop the transaction as

soon as possible if the transaction is

not granted.

DEF

SPIS

Figure 119: SPI transaction when shortcut between END and ACQUIRE is enabled

6.20.4 Pin configuration

The CSN, SCK, MOSI, and MISO signals associated with the SPI slave are mapped to physical pins according

to the configuration specified in the PSEL.CSN, PSEL.SCK, PSEL.MOSI, and PSEL.MISO registers respectively.

If the CONNECT field of any of these registers is set to Disconnected, the associated SPI slave signal will not

be connected to any physical pins.

The PSEL.CSN, PSEL.SCK, PSEL.MOSI, and PSEL.MISO registers and their configurations are only used as

long as the SPI slave is enabled, and retained only as long as the device is in System ON mode, see POWER

— Power supply on page 48 chapter for more information about power modes. When the peripheral is

disabled, the pins will behave as regular GPIOs, and use the configuration in their respective OUT bit field

and PIN_CNF[n] register. PSEL.CSN, PSEL.SCK, PSEL.MOSI, and PSEL.MISO must only be configured when

the SPI slave is disabled.

To secure correct behavior in the SPI slave, the pins used by the SPI slave must be configured in the GPIO

peripheral as described in GPIO configuration before enabling peripheral on page 307 before enabling

the SPI slave. This is to secure that the pins used by the SPI slave are driven correctly if the SPI slave itself

is temporarily disabled, or if the device temporarily enters System OFF. This configuration must be retained

in the GPIO for the selected I/Os as long as the SPI slave is to be recognized by an external SPI master.

The MISO line is set in high impedance as long as the SPI slave is not selected with CSN.

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NRF52811-QCAA-R Datasheet(PDF) 306 Page - Nordic Semiconductor