NRF52811-QCAA-R datasheet(340/444 Pages) NORDIC

340 / 444 page

Peripherals

PCLK1M

Prescaler

TIMER Core

CC[0..n]

fTIMER

Increment

MODE

PRESCALER

Counter

BITMODE

PCLK16M

TIMER

Figure 128: Block schematic for timer/counter

The timer/counter runs on the high-frequency clock source (HFCLK) and includes a four-bit (1/2X)

prescaler that can divide the timer input clock from the HFCLK controller. Clock source selection between

PCLK16M and PCLK1M is automatic according to TIMER base frequency set by the prescaler. The TIMER

base frequency is always given as 16 MHz divided by the prescaler value.

The PPI system allows a TIMER event to trigger a task of any other system peripheral of the device. The PPI

system also enables the TIMER task/event features to generate periodic output and PWM signals to any

GPIO. The number of input/outputs used at the same time is limited by the number of GPIOTE channels.

The TIMER can operate in two modes, Timer mode and Counter mode. In both modes, the TIMER is

started by triggering the START task, and stopped by triggering the STOP task. After the timer is stopped

the timer can resume timing/counting by triggering the START task again. When timing/counting is

resumed, the timer will continue from the value it had prior to being stopped.

In Timer mode, the TIMER's internal Counter register is incremented by one for every tick of the timer

frequency fTIMER as illustrated in Block schematic for timer/counter on page 340. The timer frequency is

derived from PCLK16M as shown below, using the values specified in the PRESCALER register:

fTIMER = 16 MHz / (2PRESCALER)

When fTIMER <= 1 MHz the TIMER will use PCLK1M instead of PCLK16M for reduced power consumption.

In counter mode, the TIMER's internal Counter register is incremented by one each time the COUNT task

is triggered, that is, the timer frequency and the prescaler are not utilized in counter mode. Similarly, the

COUNT task has no effect in Timer mode.

The TIMER's maximum value is configured by changing the bit-width of the timer in the BITMODE on page

345 register.

PRESCALER on page 345 and the BITMODE on page 345 must only be updated when the timer is

stopped. If these registers are updated while the TIMER is started then this may result in unpredictable

behavior.

When the timer is incremented beyond its maximum value the Counter register will overflow and the

TIMER will automatically start over from zero.

4454_140 v1.0

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NRF52811-QCAA-R Datasheet(PDF) 340 Page - Nordic Semiconductor

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