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ST10R272LT1 Datasheet(PDF) 74 Page - STMicroelectronics |
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ST10R272LT1 Datasheet(HTML) 74 Page - STMicroelectronics |
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74 / 77 page ![]() 74/77 ST10R272L - ELECTRICAL CHARACTERISTICS . 1 The pending internal hold states are cancelled and the current internal access cycle (if any) is completed. 2RSTIN pulled low by internal device during internal reset sequence. 3 The reset condition may ends here if RSTIN pin is sampled high after t72. 4 Internal pullup devices are active on the PORT0 lines. Their input level is high if the respective pin is left open, or is low if the respective pin is connected to an external pull- down device by resistive high (pullup) after t64. 5 The ST10R272L starts execution here at address 00’0000h. 6RSTOUT stays active until execution of the EINIT (End of Initialization) instruction. 7 Activation of the IO pins is controlled by software. Figure 28 External synchronous hardware reset (warm reset): Vpp high RSTIN t70 PORT1 (Demux Bus) t76 t711) PORT0 t75 5) Internal Reset Signal t73 4) t722) t74 3) ALE RD, WR RSTOUT 6) Other IOs 7) t77 t78 1 |
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