ST75C520 datasheet(12/45 Pages) STMICROELECTRONICS

12 / 45 page

V.1.2 - Interruptions

The ST75C520 can generate 5 interrupts for the

controller. The interrupt handling is made with a set

of registers located from $40 to $50.

The interruptions generated by the ST75C520

come from several different sources. Once the

ST75C520 raises an interrupt, a signal is sent to

the controller. The controller has then to process

the interrupt and clear it. The interrupt source can

be examined in the Interrupt Source Register

ITSRCR located at $50. According to this status

byte, the interrupt source can be determined.Then,

writing a zero at one of the memory location $40 to

$46 (Reset Interrupt Registers ITREST[0..6]) will

reset the corresponding interrupt (and thus ac-

knowledge it). These sources of interruptions can

be masked globally or individually using the Inter-

rupt Mask Register ITMASK located at $4F.

The interrupt sources are :

- IT0 : Error/Warning

This signifies that an error has occurred and the

error code is available in the error status byte

SYSERR. This byte can be selectively cleared by

the CSE command.

- IT2 : Tx Buffer

Each time the ST75C520 frees a buffer, this

interrupt is generated.

- IT3 : Rx Buffer

Each time the ST75C520 has filled a buffer, this

interrupt is generated.

- IT4 : Status Byte

This signifies that the status byte has changed

and must be checked by the controller.

- IT6 : Command Acknowledge

This signifies that the ST75C520 has read the last

command entered by the host, incremented the

command counter COMACK, and is ready for a

new command.

ITSRCR

D0 = 1

IT0 Pending

D2 = 1

IT2 Pending

Dn = 1

ITn Pending

ITMASK

D7 and D0 = 1 IT0 Enable D

D7 and D2 = 1 IT2 Enable D

...................... .....................

D7 and D6 = 1 IT6 Enable D

ST75C520

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