ST75C520 datasheet(5/45 Pages) STMICROELECTRONICS

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I.7 - Power Supply

Symbol

Parameter

VDD

Digital +5V (Pin 9, 25, 41). To be connected to AVDD (see below).

GND

Digital Ground (Pin 8, 24, 40). To be connected to AGNDT and AGNDR (see below).

AVDD

Analog +5V (Pin 62). To be connected to VDD (see below).

AGNDT

Analog Transmit Ground (Pin 64). To be connected to GND (see below).

AGNDR

Analog Receive Ground (Pin 59). To be connected to GND (see below).

AGNDT and AGNDR must be connected together as close as possible to the chip.

GND and AGNDR board plans should be separated, then connected together as close as possible to the

chip, at a single point. Similarly VDD and AVDD must ne connected as close as possible to the chip, at a

single point.

V.21 FLAG

DETECTOR

TONE

DETECTOR

RING

DETECTOR

V.24

INTERFACE

HANDSHAKE AND

STATUS REPORT

V.17, V.29, V.27

FAX RECEIVER

ANALOG

V.17, V.29, V.27

FAX TRANSMITTER

HDLC

DUAL RAM

INTERFACE

HDLC

MUX

DPLL

TXA1

TXA2

RXA1

RXA2

SD [0..7]

(26 to 33)

SINTR

ST75C520

II - BLOCK DIAGRAMS

II.1 - Functional Block Diagram

ST75C520

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