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EMC646SP16JS-55LL Datasheet(PDF) 31 Page - Emerging Memory & Logic Solutions Inc

Part # EMC646SP16JS-55LL
Description  4Mx16 bit CellularRAM
PDF  65 Pages
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Manufacturer  EMLSI [Emerging Memory & Logic Solutions Inc]
Direct Link  http://www.emlsi.com
Logo EMLSI - Emerging Memory & Logic Solutions Inc

EMC646SP16JS-55LL Datasheet(HTML) 31 Page - Emerging Memory & Logic Solutions Inc

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EMC646SP16J
4Mx16 CellularRAM
31
Preliminary
TIMING REQUIREMENTS
Table 13: Asynchronous READ Cycle Timing Requirements
All tests performed with outputs configured for default setting of half drive strength, (BCR[5:4] = 01b).
Note:
1. The High-Z timings measure a 100mV transition from either VOH or VOL toward VccQ/2.
2. The Low-Z timings measure a 100mV transition away from the High-Z (VccQ/2) level toward either VOH or VOL.
3. Page mode enabled only.
4. Contact EMLSI for specific timing.
Parameter
Symbol
104/83 MHz
66 MHz
Unit
Note
Min
Max
Min
Max
Address access time
tAA
70
85
ns
ADV# access time
tAADV
70
85
ns
Page access time
tAPA
20/25
25
ns
4
Address hold from ADV# HIGH
tAVH
22
ns
Address setup to ADV# HIGH
tAVS
55
ns
LB#/UB# access time
tBA
70
85
ns
LB#/UB# disable to DQ High-Z output
tBHZ
88
ns
1
LB#/UB# enable to Low-Z output
tBLZ
10
10
ns
2
Maximum CE# pulse width
tCEM
44
µs
3
CE# LOW to WAIT valid
tCEW
17.5
17.5
ns
Chip select access time
tCO
70
85
ns
CE# LOW to ADV# HIGH
tCVS
77
ns
Chip disable to DQ and WAIT High-Z output
tHZ
88
ns
1
Chip enable to Low-Z output
tLZ
10
10
ns
2
Output enable to valid output
tOE
20
20
ns
Output hold from address change
tOH
55
ns
Output disable to DQ High-Z output
tOHZ
88
ns
1
Output enable to Low-Z output
tOLZ
33
ns
2
Page READ cycle time
tPC
20/25
25
ns
4
READ cycle time
tRC
70
85
ns
ADV# pulse width LOW
tVP
57
ns



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