EMC646SP16JS-70LL datasheet(33/65 Pages) EMLSI

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EMC646SP16J

4Mx16 CellularRAM

Preliminary

Table 15: Asynchronous WRITE Cycle Timing Requirements

Note:

1. The High-Z timings measure a 100mV transition from either VOH or VOL toward VccQ/2.

2. The Low-Z timings measure a 100mV transition away from the High-Z (VccQ/2) level toward either VOH or VOL.

3. WE# Low time must be limited to tCEM (4µs).

Parameter

Symbol

104/83 MHz

66MHz

Unit

Note

Min

Max

Min

Max

Address and ADV# LOW setup time

tAS

Address HOLD from ADV# going HIGH

tAVH

Address setup to ADV# going HIGH

tAVS

Address valid to end of WRITE

tAW

LB#/UB# select to end of WRITE

tBW

CE# LOW to WAIT valid

tCEW

7.5

CE# HIGH between subsequent async operations

tCPH

CE# LOW to ADV# HIGH

tCVS

Chip enable to end of WRITE

tCW

Data HOLD from WRITE time

tDH

Data WRITE setup time

tDW

Chip disable to WAIT High-Z output

tHZ

Chip enable to Low-Z output

tLZ

End WRITE to Low-Z output

tOW

ADV# pulse width

tVP

ADV# setup to end of WRITE

tVS

WRITE cycle time

tWC

WRITE to DQ High-Z output

tWHZ

WRITE pulse width

tWP

WRITE pulse width HIGH

tWPH

WRITE recovery time

tWR

EMC646SP16JS-70LL Datasheet(PDF) 33 Page - Emerging Memory & Logic Solutions Inc

EMC646SP16JS-70LL Datasheet(HTML) 33 Page - Emerging Memory & Logic Solutions Inc

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