EMC646SP16JS-90LL datasheet(28/65 Pages) EMLSI

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EMC646SP16J

4Mx16 CellularRAM

Preliminary

Partial Array Refresh (RCR[2:0] Default = Full Array Refresh

The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the device to reduce standby current by

refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter

array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address

map.

Table 7: Address Patterns for PAR (RCR[4] = 1)

Deep Power-Down (RCR[4]) Default = DPD Disabled

The deep power-down bit enables and disables all refresh-related activity. This mode is used if the system does not require the storage

provided by the CellularRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been re-

enabled, the CellularRAM device will require 150

µs to perform an initialization procedure before normal operations can resume. Deep

power-down is enabled by setting RCR[4] = 0 and taking CE# HIGH. DPD can be enabled using CRE or the software sequence to

access the RCR. Taking CE# LOW for at least 10

µs disables DPD and sets RCR[4] = 1; it is not necessary to write to the RCR to disable

DPD. BCR and RCR values (other than RCR[4]) are preserved during DPD.

Page Mode Operation (RCR[7]) Default = Disabled

The page mode operation bit determines whether page mode is enabled for asynchronous READ operations. In the power-up default

state, page mode is disabled.

Device Identification Register

The DIDR provides information on the device manufacturer, CellularRAM generation, and the specific device configuration. Table 8

describes the bit fields in the DIDR. This register is read-only. The DIDR is accessed with CRE HIGH and A[19:18] = 01b, or through the

Table 8: Device Identification Register Mapping

RCR[2]

RCR[1]

RCR[0]

Active Section

Address Space

Size

Density

Full Die

000000h-3FFFFFh

4 Meg x 16

64Mb

One-half die

000000h-1FFFFFh

2 Meg x 16

32Mb

One-quarter of die

000000h-0FFFFFh

1 Meg x 16

16Mb

One-eighth of die

000000h-07FFFFh

512 K x 16

8Mb

None of die

0 Meg x 16

0Mb

One-half of die

200000h-3FFFFFh

2 Meg x 16

32Mb

One-quarter of die

300000h-3FFFFFh

1 Meg x 16

16Mb

One-eighth of die

380000h-3FFFFFh

512 K x 16

8Mb

Bit Field

DIDR[15]

DIDR[14:11]

DIDR[10:8]

DIDR[7:5]

DIDR[4:0]

Field name

Row Length

Device version

Device density

CellularRAM generation

Vendor ID

Length

Bit

Setting

Version

Bit

Setting

Density

Bit

Setting

Generation

Bit

Setting

Vendor

Bit

Setting

Options

256words

1st

0000b

64Mb

010b

CR 1.5

010b

EMLSI

01010b

2nd

0001b

EMC646SP16JS-90LL Datasheet(PDF) 28 Page - Emerging Memory & Logic Solutions Inc

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